14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology

Abstract

The race to deep sub-micron CMOS technology has resulted in a change in device architectures, from a planar structure to a FinFET to achieve decreased leakage, further downscaling, and better sub-threshold slope, even under a lower power supply. Downscaling trends have forced the analog semiconductor industry to move to the digital domain to maintain functionality in light of increasing short-channel effects and device mismatch. Furthermore, the main goal of the new technology is to achieve faster speed and lower cost. In leading-edge processes and design environments, conventional analog PLLs in systems-on-chip (SoCs) are being replaced by digitally operated PLLs to meet clock requirements for optimal overall system performance. While a widely used time-to-digital converter (TDC)-based digital PLL (TDC-DPLL) has a linear loop characteristic, which is simple and analogous to well-known analog PLLs, it has to overcome noise issues from TDC quantization error and phase noise from the digitally-controlled oscillator (DCO). The in-band noise floor of a TDC-DPLL is determined by the TDC resolution. Thanks to noise shaping techniques with oversampling and a pipelined architecture, noise performance can be improved. However, significant area and power must be spent to meet noise requirements. A bang-bang-based digital PLL (BB-DPLL), as the alternative type of DPLL has advantages in terms of area and power over a TDC-DPLL. However, its non-linear operation implies a longer lock time, limit-cycle noise, and high sensitivity to DCO noise. In addition, the in-band noise floor of a BB-DPLL is dominated by the input-tracking jitter, which mainly arises from the DCO noise. This paper presents a BB-DPLL in 14nm FinFET technology, combining a feed-forward delay-locked part (FFDLP) and phase-locked part (PLP) to mitigate aforementioned weaknesses.