Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062968
Wootaek Lim, Inhee Lee, D. Sylvester, D. Blaauw
Recent low-voltage design techniques have enabled dramatic improvements in miniaturization and lifetime of wireless sensor nodes [1-3]. These systems typically use a secondary battery to provide energy when the sensor is awake and operating; the battery is then recharged from a harvesting source when the sensor is asleep. In these systems, the key requirement is to minimize energy per operation of the sensor. This extends the number of operations on one battery charge and/or reduces the time to recharge the battery between awake cycles. This requirement has driven significant advances in energy efficiency [1-2] and standby power consumption [3].
{"title":"8.2 Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic","authors":"Wootaek Lim, Inhee Lee, D. Sylvester, D. Blaauw","doi":"10.1109/ISSCC.2015.7062968","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062968","url":null,"abstract":"Recent low-voltage design techniques have enabled dramatic improvements in miniaturization and lifetime of wireless sensor nodes [1-3]. These systems typically use a secondary battery to provide energy when the sensor is awake and operating; the battery is then recharged from a harvesting source when the sensor is asleep. In these systems, the key requirement is to minimize energy per operation of the sensor. This extends the number of operations on one battery charge and/or reduces the time to recharge the battery between awake cycles. This requirement has driven significant advances in energy efficiency [1-2] and standby power consumption [3].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127474309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062959
Mario Sako, Y. Watanabe, T. Nakajima, Jumpei Sato, K. Muraoka, M. Fujiu, F. Kouno, M. Nakagawa, M. Masuda, Koji Kato, Yuri Terada, Y. Shimizu, M. Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, M. Kamoshida, M. Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita
The demand for high-throughput NAND Flash memory systems for mobile applications such as smart phones, tablets, and laptop PCs with solid-state drives (SSDs) has been growing recently. To obtain higher throughput, systems employ multiple NAND Flash memories operating simultaneously in parallel. The available power for a mobile device is severely restricted and the peak total operating current may be high enough to cause large supply-voltage drop or even an unexpected system shutdown. Therefore it is important for NAND Flash memories to reduce operating power and peak operating current.
{"title":"7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology","authors":"Mario Sako, Y. Watanabe, T. Nakajima, Jumpei Sato, K. Muraoka, M. Fujiu, F. Kouno, M. Nakagawa, M. Masuda, Koji Kato, Yuri Terada, Y. Shimizu, M. Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, M. Kamoshida, M. Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita","doi":"10.1109/ISSCC.2015.7062959","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062959","url":null,"abstract":"The demand for high-throughput NAND Flash memory systems for mobile applications such as smart phones, tablets, and laptop PCs with solid-state drives (SSDs) has been growing recently. To obtain higher throughput, systems employ multiple NAND Flash memories operating simultaneously in parallel. The available power for a mobile device is severely restricted and the peak total operating current may be high enough to cause large supply-voltage drop or even an unexpected system shutdown. Therefore it is important for NAND Flash memories to reduce operating power and peak operating current.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115573155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063101
T. Shibasaki, Y. Tsunoda, H. Oku, S. Ide, Toshihiko Mori, Y. Koyanagi, Kazuhiro Tanaka, T. Ishihara, H. Tamura
To meet increasing demands for server computational power, high-density, multilane links with a data rate exceeding 25Gb/s/lane are needed. An optical transceiver with a retiming capability would significantly enhance the usability of the link by extending the reach. Such optical transceivers should operate without an external clock source since a small form factor is imperative. The optical link we develop has a four-lane configuration that consists of an electrical-to-optical (E/O) converter and an optical-to-electrical (O/E) convertor (Fig. 22.7.1). Both the E/O and O/E convertors are equipped with a per-lane reference-less clock-and-data recovery (CDR) circuit that enables independent operation of each lane. The transceiver pitch is 250μm/lane, which matches the fiber pitch of the optical-fiber array used in the link. Since the jitter added by the CDR should be minimized in retimer applications, an LC-VCO is a preferable choice for clock-signal generation. At this transceiver pitch, however, the coupling through mutual inductances between LC tanks has a significant impact on the CDR characteristics. To address this concern, we analyze the impact of inter-VCO coupling and design the CDR so that the coupling does not affect the CDR performance. Each lane of the E/O convertor consists of a continuous-time linear equalizer (CTLE), a CDR, and a VCSEL driver with a two-tap feed-forward equalizer (FFE) (Fig. 22.7.1). Each lane of the O/E convertor has a trans-impedance amplifier (TIA) stage followed by a limiting amplifier (LA), a CDR, and an electrical-line driver with a two-tap FFE. All the CDRs have an identical design consisting of a flip-flop for the data decision, a selector for bypass-mode operation, a Pottbacker type phase-frequency detector (PFD) [1], a charge pump (CP), a lag-lead filter, and a quadrature LC-VCO (QVCO). During the bypass mode, the CDR loop is set into a power-down mode where the VCO does not oscillate.
{"title":"22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS","authors":"T. Shibasaki, Y. Tsunoda, H. Oku, S. Ide, Toshihiko Mori, Y. Koyanagi, Kazuhiro Tanaka, T. Ishihara, H. Tamura","doi":"10.1109/ISSCC.2015.7063101","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063101","url":null,"abstract":"To meet increasing demands for server computational power, high-density, multilane links with a data rate exceeding 25Gb/s/lane are needed. An optical transceiver with a retiming capability would significantly enhance the usability of the link by extending the reach. Such optical transceivers should operate without an external clock source since a small form factor is imperative. The optical link we develop has a four-lane configuration that consists of an electrical-to-optical (E/O) converter and an optical-to-electrical (O/E) convertor (Fig. 22.7.1). Both the E/O and O/E convertors are equipped with a per-lane reference-less clock-and-data recovery (CDR) circuit that enables independent operation of each lane. The transceiver pitch is 250μm/lane, which matches the fiber pitch of the optical-fiber array used in the link. Since the jitter added by the CDR should be minimized in retimer applications, an LC-VCO is a preferable choice for clock-signal generation. At this transceiver pitch, however, the coupling through mutual inductances between LC tanks has a significant impact on the CDR characteristics. To address this concern, we analyze the impact of inter-VCO coupling and design the CDR so that the coupling does not affect the CDR performance. Each lane of the E/O convertor consists of a continuous-time linear equalizer (CTLE), a CDR, and a VCSEL driver with a two-tap feed-forward equalizer (FFE) (Fig. 22.7.1). Each lane of the O/E convertor has a trans-impedance amplifier (TIA) stage followed by a limiting amplifier (LA), a CDR, and an electrical-line driver with a two-tap FFE. All the CDRs have an identical design consisting of a flip-flop for the data decision, a selector for bypass-mode operation, a Pottbacker type phase-frequency detector (PFD) [1], a charge pump (CP), a lag-lead filter, and a quadrature LC-VCO (QVCO). During the bypass mode, the CDR loop is set into a power-down mode where the VCO does not oscillate.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116547709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062975
T. Georgantas, K. Vavelidis, N. Haralabidis, S. Bouras, I. Vassiliou, C. Kapnistis, Y. Kokolakis, H. Peyravi, G. Theodoratos, K. Vryssas, N. Kanakaris, Christos Kokozidis, Spyros Kavvadias, S. Plevridis, P. Mudge, I. Elgorriaga, A. Kyranas, Spyridon Liolis, Eleni-Sotiria Kytonaki, G. Konstantopoulos, P. Robogiannakis, K. Tsilipanos, Michael Margaras, P. Betzios, R. Magoon, Nias Bouras, M. Rofougaran, R. Rofougaran
To support increased device functionality and higher data-rates in LTE-enabled systems, while improving user experience and usage time, there is a need to reduce RFIC size and power consumption without degrading performance, while maintaining backward compatibility with legacy 2G/3G systems [1]. This paper introduces a 13mm2, 40nm CMOS 2G/HSPA+/TDSCDMA/UE cat. 4 transceiver that consumes 36/65mA battery-referenced current in 3G/LTE20 modes (B1, -50dBm TX, -60dBm RX). This is achieved in part by employing a multiport single-core LNA with a multitap inductor and a current-mode-driven single-core transmit mixer. Baseband-assisted calibration techniques help achieve <;1.2% RX EVM in LTE20 and >60dBm IIP2 in all bands. To save on platform area and cost, the RFIC supports single-ended LNAs, 32kHz clock generation, and free-running XTAL operation. TX SAW filters are not required.
{"title":"9.1 A 13mm2 40nm multiband GSM/EDGE/HSPA+/TDSCDMA/LTE transceiver","authors":"T. Georgantas, K. Vavelidis, N. Haralabidis, S. Bouras, I. Vassiliou, C. Kapnistis, Y. Kokolakis, H. Peyravi, G. Theodoratos, K. Vryssas, N. Kanakaris, Christos Kokozidis, Spyros Kavvadias, S. Plevridis, P. Mudge, I. Elgorriaga, A. Kyranas, Spyridon Liolis, Eleni-Sotiria Kytonaki, G. Konstantopoulos, P. Robogiannakis, K. Tsilipanos, Michael Margaras, P. Betzios, R. Magoon, Nias Bouras, M. Rofougaran, R. Rofougaran","doi":"10.1109/ISSCC.2015.7062975","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062975","url":null,"abstract":"To support increased device functionality and higher data-rates in LTE-enabled systems, while improving user experience and usage time, there is a need to reduce RFIC size and power consumption without degrading performance, while maintaining backward compatibility with legacy 2G/3G systems [1]. This paper introduces a 13mm2, 40nm CMOS 2G/HSPA+/TDSCDMA/UE cat. 4 transceiver that consumes 36/65mA battery-referenced current in 3G/LTE20 modes (B1, -50dBm TX, -60dBm RX). This is achieved in part by employing a multiport single-core LNA with a multitap inductor and a current-mode-driven single-core transmit mixer. Baseband-assisted calibration techniques help achieve <;1.2% RX EVM in LTE20 and >60dBm IIP2 in all bands. To save on platform area and cost, the RFIC supports single-ended LNAs, 32kHz clock generation, and free-running XTAL operation. TX SAW filters are not required.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122819015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063027
Teng Yang, Doyun Kim, P. Kinget, Mingoo Seok
SRAM register files have sensitive circuitry and often operate with high switching activity and at high temperature. This makes them particularly vulnerable to aging by negative-bias temperature instability (NBTI) degradation of their PMOS devices. We propose a technique to sense this aging degradation; it is an in-situ technique sensing the threshold voltage (Vt) of PMOSs directly in bitcells, and can operate in-field, thanks to the ability to sense V, robustly across temperature and voltage variations. This technique can be foundational for several dynamic reliability management (DRM) approaches, including: 1) sensing V, values periodically (e.g., every several months) for evaluating the amount and the rate of NBTI degradation; 2) sensing V, differences between two PMOSs in a bitcell to determine their strength skew and to estimate the minimum functional voltage (VMIN) degradation; and, 3) using the skew information across bitcells to create recovery vectors, which can be used to recover the aged PMOSs and thereby rebalance the skews. Existing in-situ techniques using ring oscillators or current sensors to sense bitcell reliability and performance cannot support in-field operation, which is a critical issue for DRM since it is impractical to control environmental parameters, particularly temperature, during sensing.
{"title":"14.7 In-situ techniques for in-field sensing of NBTI degradation in an SRAM register file","authors":"Teng Yang, Doyun Kim, P. Kinget, Mingoo Seok","doi":"10.1109/ISSCC.2015.7063027","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063027","url":null,"abstract":"SRAM register files have sensitive circuitry and often operate with high switching activity and at high temperature. This makes them particularly vulnerable to aging by negative-bias temperature instability (NBTI) degradation of their PMOS devices. We propose a technique to sense this aging degradation; it is an in-situ technique sensing the threshold voltage (Vt) of PMOSs directly in bitcells, and can operate in-field, thanks to the ability to sense V, robustly across temperature and voltage variations. This technique can be foundational for several dynamic reliability management (DRM) approaches, including: 1) sensing V, values periodically (e.g., every several months) for evaluating the amount and the rate of NBTI degradation; 2) sensing V, differences between two PMOSs in a bitcell to determine their strength skew and to estimate the minimum functional voltage (VMIN) degradation; and, 3) using the skew information across bitcells to create recovery vectors, which can be used to recover the aged PMOSs and thereby rebalance the skews. Existing in-situ techniques using ring oscillators or current sensors to sense bitcell reliability and performance cannot support in-field operation, which is a critical issue for DRM since it is impractical to control environmental parameters, particularly temperature, during sensing.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114553253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063050
E. Karl, Z. Guo, J. Conary, Jeffrey L. Miller, Y. Ng, Satyanand Nalam, Daeyeon Kim, J. Keane, U. Bhattacharya, Kevin Zhang
The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (VMIN) of a design, often leading to the introduction of separate voltage supplies for on-die memory. Additional supplies increase platform cost, and operating memory at higher voltage leads to increased power consumption. The introduction of trigate devices at the 22nm technology node delivered superior short channel effects and subthreshold slope relative to existing bulk planar device technology enabling reduction in threshold voltage within a fixed leakage constraint. Lower transistor Vth, improvements to random device variability, and assist circuits to overcome device-size quantization enabled a >150mV reduction in SRAM VMIN [1]. At the 14nm technology node, FinFET device-size quantization remains a challenge for compact 6T SRAM bitcells with minimum-size transistors. Careful co-optimization between technology and design of memory-assist circuits is required in order to deliver dense, low-power memory operation at low voltages. In this paper, we present an 84Mb SRAM array design with wide-voltage-range operation in a 14nm logic technology featuring 2nd-generation FinFET transistors.
{"title":"17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology","authors":"E. Karl, Z. Guo, J. Conary, Jeffrey L. Miller, Y. Ng, Satyanand Nalam, Daeyeon Kim, J. Keane, U. Bhattacharya, Kevin Zhang","doi":"10.1109/ISSCC.2015.7063050","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063050","url":null,"abstract":"The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (VMIN) of a design, often leading to the introduction of separate voltage supplies for on-die memory. Additional supplies increase platform cost, and operating memory at higher voltage leads to increased power consumption. The introduction of trigate devices at the 22nm technology node delivered superior short channel effects and subthreshold slope relative to existing bulk planar device technology enabling reduction in threshold voltage within a fixed leakage constraint. Lower transistor Vth, improvements to random device variability, and assist circuits to overcome device-size quantization enabled a >150mV reduction in SRAM VMIN [1]. At the 14nm technology node, FinFET device-size quantization remains a challenge for compact 6T SRAM bitcells with minimum-size transistors. Careful co-optimization between technology and design of memory-assist circuits is required in order to deliver dense, low-power memory operation at low voltages. In this paper, we present an 84Mb SRAM array design with wide-voltage-range operation in a 14nm logic technology featuring 2nd-generation FinFET transistors.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"397 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122184647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062931
H. Li, Jinuk Luke Shin, G. Konstadinidis, F. Schumacher, V. Krishnaswamy, Hoyeol Cho, Sudesna Dash, R. Masleid, Chaoyang Zheng, Yuanjung David Lin, P. Loewenstein, Heechoul Park, V. Srinivasan, Dawei Huang, C. Hwang, W. Hsu, C. McAllister
The SPARC M7 processor delivers more than 3x throughput performance improvement over its predecessor SPARC M6 for commercial applications. It introduces new design features, such as the S4 core, a 64MB L3 cache subsystem with application data integrity, a low-latency, high-throughput on-chip network (OCN), a database analytic accelerator (DAX), fine-grain adaptive power management and 1.5× higher SerDes I/O bandwidth for memory, coherency and system interfaces (Fig. 4.2.1) [1]. The enhancements in the S4 core over the S3 core [2] include a new L2 cache scheme, support for visual instruction set (VIS) extensions, virtual address masking and user-level synchronization instructions to provide continuous single-thread performance improvement for SPARC processors since SPARC T4. In addition, a hierarchical modular approach, called SPARC cache cluster (SCC), is used for the core-L2-L3 cache system. Within the SCC, all four cores share a single 256KB L2 instruction cache and each core pair has its own 256KB L2 data cache. The L2 caches are organized as 2-banks and 8-ways to deliver greater than 1TB/s bandwidth to the four cores. This L2 system delivers 2× more throughput for each core with 1.5x increase in size and the same latency as the previous generation L2 cache scheme. The L2 caches connect to an 8MB, 8-way set-associative partitioned L3 cache. Having a localized L3 cache within each SCC reduces L3 latency by 25%. The chip contains eight SCCs for a total of 32-cores with 256 threads and a 64MB L3 cache with 1.6TB/S bandwidth. In order to support the bandwidth and latency requirements from 256 threads and other system agents, the OCN architecture is implemented in place of a crossbar based network used in previous SPARC processors. Each SCC connects to the OCN, which in turn connects to four on-chip memory controllers (MCUs), coherency systems and eight database analytic accelerator (DAX) engines. The SPARC M7 introduces a customized DAX engine in an effort to optimize performance for Oracle databases. Eight DAX engines handle simple query predicates, decompression, message passing and interrupts across cluster nodes. This query accelerator provides up to 10x better performance for single stream decompression.
{"title":"4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor","authors":"H. Li, Jinuk Luke Shin, G. Konstadinidis, F. Schumacher, V. Krishnaswamy, Hoyeol Cho, Sudesna Dash, R. Masleid, Chaoyang Zheng, Yuanjung David Lin, P. Loewenstein, Heechoul Park, V. Srinivasan, Dawei Huang, C. Hwang, W. Hsu, C. McAllister","doi":"10.1109/ISSCC.2015.7062931","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062931","url":null,"abstract":"The SPARC M7 processor delivers more than 3x throughput performance improvement over its predecessor SPARC M6 for commercial applications. It introduces new design features, such as the S4 core, a 64MB L3 cache subsystem with application data integrity, a low-latency, high-throughput on-chip network (OCN), a database analytic accelerator (DAX), fine-grain adaptive power management and 1.5× higher SerDes I/O bandwidth for memory, coherency and system interfaces (Fig. 4.2.1) [1]. The enhancements in the S4 core over the S3 core [2] include a new L2 cache scheme, support for visual instruction set (VIS) extensions, virtual address masking and user-level synchronization instructions to provide continuous single-thread performance improvement for SPARC processors since SPARC T4. In addition, a hierarchical modular approach, called SPARC cache cluster (SCC), is used for the core-L2-L3 cache system. Within the SCC, all four cores share a single 256KB L2 instruction cache and each core pair has its own 256KB L2 data cache. The L2 caches are organized as 2-banks and 8-ways to deliver greater than 1TB/s bandwidth to the four cores. This L2 system delivers 2× more throughput for each core with 1.5x increase in size and the same latency as the previous generation L2 cache scheme. The L2 caches connect to an 8MB, 8-way set-associative partitioned L3 cache. Having a localized L3 cache within each SCC reduces L3 latency by 25%. The chip contains eight SCCs for a total of 32-cores with 256 threads and a 64MB L3 cache with 1.6TB/S bandwidth. In order to support the bandwidth and latency requirements from 256 threads and other system agents, the OCN architecture is implemented in place of a crossbar based network used in previous SPARC processors. Each SCC connects to the OCN, which in turn connects to four on-chip memory controllers (MCUs), coherency systems and eight database analytic accelerator (DAX) engines. The SPARC M7 introduces a customized DAX engine in an effort to optimize performance for Oracle databases. Eight DAX engines handle simple query predicates, decompression, message passing and interrupts across cluster nodes. This query accelerator provides up to 10x better performance for single stream decompression.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129522352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063068
Run Chen, H. Hashemi
The demand for increased wireless data throughput in future wireless communication and the lack of available wide contiguous frequency bands inspire the concept of aggregating multiple frequency bands in a Software-Defined Radio (SDR). A major challenge for such an SDR receiver is maintaining a high dynamic range in the presence of various desired and undesired signals spread over a wide frequency range. This paper introduces a receiver architecture that allows the RF front-end to be configured with various filtering profiles depending on signal scenarios while supporting intra-band multichannel carrier aggregation (contiguous and non-contiguous) with only one frequency synthesizer.
{"title":"19.3 Reconfigurable SDR receiver with enhanced front-end frequency selectivity suitable for intra-band and inter-band carrier aggregation","authors":"Run Chen, H. Hashemi","doi":"10.1109/ISSCC.2015.7063068","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063068","url":null,"abstract":"The demand for increased wireless data throughput in future wireless communication and the lack of available wide contiguous frequency bands inspire the concept of aggregating multiple frequency bands in a Software-Defined Radio (SDR). A major challenge for such an SDR receiver is maintaining a high dynamic range in the presence of various desired and undesired signals spread over a wide frequency range. This paper introduces a receiver architecture that allows the RF front-end to be configured with various filtering profiles depending on signal scenarios while supporting intra-band multichannel carrier aggregation (contiguous and non-contiguous) with only one frequency synthesizer.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129562677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
All-digital phase-locked loops (ADPLLs) offer faster locking time, easier portability and better performance in advanced semiconductor processes as compared to analog PLLs. Advanced FinFET devices exhibit better gm and ION than planar devices [1], but they are offered only in a limited number of device sizes, thus precluding their use in traditional analog design styles. In an ADPLL, the transistors are used as switches with little regard to their linear analog properties. Hence, ADPLL performance should improve with the adoption of FinFET devices. Inverter delay in a 16nm FinFET process is less than half of that in a 28nm planar process, improving in-band phase noise (PN) by around 6dB [2]. Ring-type digitally controlled oscillators (DCOs) provide wide frequency tuning range (FTR), but poor PN performance degrades the ADPLL figure of merit (FoM) [3]. Achieving an FoM better than -225dB using a ring DCO is a challenge. In this work, we presenta 0.25-to-4GHz, 1.22ps integrated jitter and -228.6dB FoM fractional-N ADPLL with spread-spectrum clocking (SSC) capability in 16nm FinFET CMOS.
{"title":"14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S","authors":"Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, R. Staszewski","doi":"10.1109/ISSCC.2015.7063025","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063025","url":null,"abstract":"All-digital phase-locked loops (ADPLLs) offer faster locking time, easier portability and better performance in advanced semiconductor processes as compared to analog PLLs. Advanced FinFET devices exhibit better gm and ION than planar devices [1], but they are offered only in a limited number of device sizes, thus precluding their use in traditional analog design styles. In an ADPLL, the transistors are used as switches with little regard to their linear analog properties. Hence, ADPLL performance should improve with the adoption of FinFET devices. Inverter delay in a 16nm FinFET process is less than half of that in a 28nm planar process, improving in-band phase noise (PN) by around 6dB [2]. Ring-type digitally controlled oscillators (DCOs) provide wide frequency tuning range (FTR), but poor PN performance degrades the ADPLL figure of merit (FoM) [3]. Achieving an FoM better than -225dB using a ring DCO is a challenge. In this work, we presenta 0.25-to-4GHz, 1.22ps integrated jitter and -228.6dB FoM fractional-N ADPLL with spread-spectrum clocking (SSC) capability in 16nm FinFET CMOS.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128481890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062953
F. Mochizuki, K. Kagawa, S. Okihara, M. Seo, Bo Zhang, T. Takasawa, K. Yasutomi, S. Kawahito
Ultra-high-speed cameras are a powerful tool for biology as well as physics and mechanics to analyze the process of ultra-high-speed phenomena. The frame rate of the state-of-the-art burst-readout ultra-high-speed silicon imagers has reached approximately 20Mfps [1,2]. To observe faster phenomena such as plasma generation in laser processing, the state of electrons in a chemical reaction, and so on, much faster cameras are desired. There are several factors that prevent the speed-up of the ultra-high-speed imager: high gate control voltages and high power dissipation for high-efficiency multi-stage charge transfer in CCD imagers, and the current density limit of the power and ground lines and RC-constant of the vertical readout lines in CMOS imagers. Computational imaging can be a promising option to break the design limit of solid-state ultra-high-speed imagers. Several dedicated CMOS imagers have been demonstrated [3,4]. This paper presents a demonstration of a single-chip ultra-high-speed multi-aperture CMOS imager based on compressive sampling. The imager performs single-shot burst-readout image acquisition at a frame rate of 200Mfps.
{"title":"6.4 Single-shot 200Mfps 5×3-aperture compressive CMOS imager","authors":"F. Mochizuki, K. Kagawa, S. Okihara, M. Seo, Bo Zhang, T. Takasawa, K. Yasutomi, S. Kawahito","doi":"10.1109/ISSCC.2015.7062953","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062953","url":null,"abstract":"Ultra-high-speed cameras are a powerful tool for biology as well as physics and mechanics to analyze the process of ultra-high-speed phenomena. The frame rate of the state-of-the-art burst-readout ultra-high-speed silicon imagers has reached approximately 20Mfps [1,2]. To observe faster phenomena such as plasma generation in laser processing, the state of electrons in a chemical reaction, and so on, much faster cameras are desired. There are several factors that prevent the speed-up of the ultra-high-speed imager: high gate control voltages and high power dissipation for high-efficiency multi-stage charge transfer in CCD imagers, and the current density limit of the power and ground lines and RC-constant of the vertical readout lines in CMOS imagers. Computational imaging can be a promising option to break the design limit of solid-state ultra-high-speed imagers. Several dedicated CMOS imagers have been demonstrated [3,4]. This paper presents a demonstration of a single-chip ultra-high-speed multi-aperture CMOS imager based on compressive sampling. The imager performs single-shot burst-readout image acquisition at a frame rate of 200Mfps.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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