Threshold Voltage Shift in a-Si:H Thin film Transistors under ESD stress Conditions

Abstract

We present physical insights into the instability behavior of hydrogenated amorphous TFTs under ESD stress using real-time current-voltage and capacitance-voltage characterization. A threshold voltage increase under moderate stress and a recovery under high stress is investigated. Impact of gate-bias and device dimension is explored. Physics of gate-bias annealing and an associated device recovery is explored. Finally, we investigate the instability behavior in a-Si:H gated diodes and explore the role of self-heating on their reliability.