Sub-nanosecond Reverse Recovery Measurement for ESD Devices

Abstract

A method to measure sub-nanosecond reverse recovery in wafer-level test structures is presented. The setup uses a transmission line pulse generator with a time-domain through connection to measure the device-under-test current. The setup is used to measure reverse recovery in a 65-nm CMOS ESD diode, and it is found that a quasi-static compact model does not accurately describe the observed transient. A non-quasi-static charge control model is used to accurately simulate both the reverse recovery and the forward bias behavior.