Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128338
Jeffrey Zhang, Antai Xu, D. Gitlin, Desmond Yeo
As the automotive industry moves toward autonomous driving and zero defect, production burn-in becomes more important, so is optimizing its efficiency. Although dynamic burn-in is considered more efficient than static in theory, there have been very few reported studies based on actual data. This work analyzes production burn-in data of ~34k units produced using TSMC’s 16nm process, and shows that dynamic burn-in is approximately >4x as effective as static burn-in in catching early silicon failures
{"title":"Dynamic vs Static Burn-in for 16nm Production","authors":"Jeffrey Zhang, Antai Xu, D. Gitlin, Desmond Yeo","doi":"10.1109/IRPS45951.2020.9128338","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128338","url":null,"abstract":"As the automotive industry moves toward autonomous driving and zero defect, production burn-in becomes more important, so is optimizing its efficiency. Although dynamic burn-in is considered more efficient than static in theory, there have been very few reported studies based on actual data. This work analyzes production burn-in data of ~34k units produced using TSMC’s 16nm process, and shows that dynamic burn-in is approximately >4x as effective as static burn-in in catching early silicon failures","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123709201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128844
Clement Huang, A. Juan, K. Su
Stress Induced Voiding (SIV) is strongly influenced by electroplating copper process (ECP) hardware setting: edge bevel removal (EBR, post plating cell of ECP hardware). The study indicated that more EBR will induce poor SIV performance. This phenomenon could be explained by the radius of curvature of a 300 mm patterned wafer. More outliers was observed at the higher level via. This suggested that the thermally induced stress in the via was increased with higher metallization layers. Regarding to the impact of metal width, only the widest metal width plus more EBR has highest RC drift, suggested that wider metal provides a sufficient vacancy source to form voids by more compressive stress gradient distribution beneath the via then cause higher RC drift.
{"title":"Stress Induced Voiding Behavior of Electroplated Copper Thin Films in Highly Scaled Cu/low-k interconnects","authors":"Clement Huang, A. Juan, K. Su","doi":"10.1109/IRPS45951.2020.9128844","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128844","url":null,"abstract":"Stress Induced Voiding (SIV) is strongly influenced by electroplating copper process (ECP) hardware setting: edge bevel removal (EBR, post plating cell of ECP hardware). The study indicated that more EBR will induce poor SIV performance. This phenomenon could be explained by the radius of curvature of a 300 mm patterned wafer. More outliers was observed at the higher level via. This suggested that the thermally induced stress in the via was increased with higher metallization layers. Regarding to the impact of metal width, only the widest metal width plus more EBR has highest RC drift, suggested that wider metal provides a sufficient vacancy source to form voids by more compressive stress gradient distribution beneath the via then cause higher RC drift.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126849369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128317
T. Lee, K. Yamane, L. Y. Hau, R. Chao, N. L. Chung, V. B. Naik, K. Sivabalan, J. Kwon, Jia Hao Lim, W. Neo, K. Khua, N. Thiyagarajah, S. H. Jang, B. Behin-Aein, E. Toh, Y. Otani, D. Zeng, N. Balasankaran, L. C. Goh, Timothy Ling, J. Hwang, Lei Zhang, Rachel Low, Soon Leng Tan, C. Seet, J. W. Ting, Stanley Ong, Y. You, S. Woo, E. Quek, S. Siah
In the era of embedded MRAM (eMRAM) technology evolution for the replacement of eFlash and SRAM, the correlation between magnetic immunity (MI) and eMRAM reliability must be well understood to realize the mass production. In this paper, we have classified the types of MIs and also established the MI guidelines for eMRAM product reliability for the first time. From 40Mb eMRAM package-level data, our proposed MI specifications guarantee the 10 years of reliability at operating temperatures ranging from -40°C to 150°C, which covers all industrial-grade and automotive-grade-1 applications.
{"title":"Magnetic Immunity Guideline for Embedded MRAM Reliability to Realize Mass Production","authors":"T. Lee, K. Yamane, L. Y. Hau, R. Chao, N. L. Chung, V. B. Naik, K. Sivabalan, J. Kwon, Jia Hao Lim, W. Neo, K. Khua, N. Thiyagarajah, S. H. Jang, B. Behin-Aein, E. Toh, Y. Otani, D. Zeng, N. Balasankaran, L. C. Goh, Timothy Ling, J. Hwang, Lei Zhang, Rachel Low, Soon Leng Tan, C. Seet, J. W. Ting, Stanley Ong, Y. You, S. Woo, E. Quek, S. Siah","doi":"10.1109/IRPS45951.2020.9128317","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128317","url":null,"abstract":"In the era of embedded MRAM (eMRAM) technology evolution for the replacement of eFlash and SRAM, the correlation between magnetic immunity (MI) and eMRAM reliability must be well understood to realize the mass production. In this paper, we have classified the types of MIs and also established the MI guidelines for eMRAM product reliability for the first time. From 40Mb eMRAM package-level data, our proposed MI specifications guarantee the 10 years of reliability at operating temperatures ranging from -40°C to 150°C, which covers all industrial-grade and automotive-grade-1 applications.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"17 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126962847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129124
R. Wuytens, S. Santermans, Mihir Gupta, B. D. Bois, S. Severi, L. Lagae, W. Roy, K. Martens
Drift is the most well-known reliability issue of electrolytically gated ISFETs and bioFET sensors. The shift of the threshold voltage with time of electrolytically gated FETs compromises the reliability of these sensors. Notwithstanding, relatively little work has been done to understand the issue. We distinguish two drift regimes which occur at room temperature and at approximately zero gate bias conditions: a strong initial transient drift (81-144mV) and a weaker eventual drift (-0.6 - - 0.8mV/hr), and we elaborate on the strong initial transient drift. We compare drift in SiO2, SiON and HfO2 FETs and discuss kinetics, area and salinity dependence. An SC1 preclean shows no significant impact on transient drift precluding a role of siloxane oxidation in initial drift. Two hypotheses regarding the cause of the initial drift are tested with tailored experiments: gate oxide hydration and gate oxide contamination. We find contamination to most adequately explain our observations. For bioFETs, the addition of a Self-Assembled Monolayer (SAM) does not have a large impact on initial drift whereas a DNA graft strongly reduces the initial drift.
{"title":"Two-Regime Drift in Electrolytically Gated FETs and BioFETs","authors":"R. Wuytens, S. Santermans, Mihir Gupta, B. D. Bois, S. Severi, L. Lagae, W. Roy, K. Martens","doi":"10.1109/IRPS45951.2020.9129124","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129124","url":null,"abstract":"Drift is the most well-known reliability issue of electrolytically gated ISFETs and bioFET sensors. The shift of the threshold voltage with time of electrolytically gated FETs compromises the reliability of these sensors. Notwithstanding, relatively little work has been done to understand the issue. We distinguish two drift regimes which occur at room temperature and at approximately zero gate bias conditions: a strong initial transient drift (81-144mV) and a weaker eventual drift (-0.6 - - 0.8mV/hr), and we elaborate on the strong initial transient drift. We compare drift in SiO2, SiON and HfO2 FETs and discuss kinetics, area and salinity dependence. An SC1 preclean shows no significant impact on transient drift precluding a role of siloxane oxidation in initial drift. Two hypotheses regarding the cause of the initial drift are tested with tailored experiments: gate oxide hydration and gate oxide contamination. We find contamination to most adequately explain our observations. For bioFETs, the addition of a Self-Assembled Monolayer (SAM) does not have a large impact on initial drift whereas a DNA graft strongly reduces the initial drift.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128807719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129158
C. Premachandran, S. Cimino, M. Prabhu
During metal/dielectric plasma processing for the back end of the line (BEOL), degradation of the transistor gate oxide may occur due to the plasma discharge current. This degradation can create a functional failure or lead to future reliability issues. Diodes of a specific size are incorporated into the chip to protect from plasma induced damage (PID) during the BEOL processing. In 3D integrated circuits (IC) additional processes such as through silicon via (TSV) etching and backside redistribution layer (RDL) are accounted for in deciding the diode size. Additional diode protection structure is also used for electrostatic discharge (ESD) damage during fab/assembly. In this study, a bidirectional diode is proposed to protect the transistor gate oxide from both PID and ESD during the 3D IC integration process. The combined protection diode addresses PID due to front and back side processes and ESD during chip to chip/wafer to wafer bonding process.
{"title":"Efficient Bidirectional protection structure for Plasma induced damage (PID) and Electrostatic discharge (ESD) for 3D IC Integration","authors":"C. Premachandran, S. Cimino, M. Prabhu","doi":"10.1109/IRPS45951.2020.9129158","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129158","url":null,"abstract":"During metal/dielectric plasma processing for the back end of the line (BEOL), degradation of the transistor gate oxide may occur due to the plasma discharge current. This degradation can create a functional failure or lead to future reliability issues. Diodes of a specific size are incorporated into the chip to protect from plasma induced damage (PID) during the BEOL processing. In 3D integrated circuits (IC) additional processes such as through silicon via (TSV) etching and backside redistribution layer (RDL) are accounted for in deciding the diode size. Additional diode protection structure is also used for electrostatic discharge (ESD) damage during fab/assembly. In this study, a bidirectional diode is proposed to protect the transistor gate oxide from both PID and ESD during the 3D IC integration process. The combined protection diode addresses PID due to front and back side processes and ESD during chip to chip/wafer to wafer bonding process.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129917548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129631
S. Bahl, Francisco Baltazar, Yong Xie
The determination of switching lifetime for GaN products is a very timely and important topic, both for the assurance of reliable operation in application, and for the development of standardized industry approaches. The challenges faced are the complexity of the switching transition, the dependence of the stress on the application circuit, and the lack of a broad modeling approach. These have prevented the realization of a "develop once, use broadly" methodology. We show, for the first time, an approach that addresses these issues and results in a generalized methodology to determine switching stress and calculate lifetime. The model created directly uses the fundamental stressors of voltage, current and time from the switching waveform. Using this approach, TI GaN product is shown to be highly reliable under applicationuse conditions.
{"title":"A Generalized Approach to Determine the Switching Lifetime of a GaN FET","authors":"S. Bahl, Francisco Baltazar, Yong Xie","doi":"10.1109/IRPS45951.2020.9129631","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129631","url":null,"abstract":"The determination of switching lifetime for GaN products is a very timely and important topic, both for the assurance of reliable operation in application, and for the development of standardized industry approaches. The challenges faced are the complexity of the switching transition, the dependence of the stress on the application circuit, and the lack of a broad modeling approach. These have prevented the realization of a \"develop once, use broadly\" methodology. We show, for the first time, an approach that addresses these issues and results in a generalized methodology to determine switching stress and calculate lifetime. The model created directly uses the fundamental stressors of voltage, current and time from the switching waveform. Using this approach, TI GaN product is shown to be highly reliable under applicationuse conditions.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126692058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128846
Evelyn Landman, Noam Brousard, Tamar Naishlos
This paper describes a deep data approach to reliability monitoring in advanced electronics, based on degradation as a precursor for failure. By applying machine learning algorithms and analytics to data created by on-chip monitoring IPs (Agents), IC/system health and performance can be continuously monitored, at all stages of the product lifecycle. Realtime degradation analysis of critical parameters and failure mechanisms, under field conditions and application environments, points to the underlying Physics of Failure, which in turn allows to estimate the time to failure. Users are alerted on faults in advance, via a cloud-based analytics platform, and can take corrective action to prevent failures. The future of reliability physics and engineering is fundamentally shifting from accelerated lifetime tests to in-field failure prediction.
{"title":"A novel approach to in-field, in-mission reliability monitoring based on Deep Data","authors":"Evelyn Landman, Noam Brousard, Tamar Naishlos","doi":"10.1109/IRPS45951.2020.9128846","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128846","url":null,"abstract":"This paper describes a deep data approach to reliability monitoring in advanced electronics, based on degradation as a precursor for failure. By applying machine learning algorithms and analytics to data created by on-chip monitoring IPs (Agents), IC/system health and performance can be continuously monitored, at all stages of the product lifecycle. Realtime degradation analysis of critical parameters and failure mechanisms, under field conditions and application environments, points to the underlying Physics of Failure, which in turn allows to estimate the time to failure. Users are alerted on faults in advance, via a cloud-based analytics platform, and can take corrective action to prevent failures. The future of reliability physics and engineering is fundamentally shifting from accelerated lifetime tests to in-field failure prediction.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130679919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128951
Shin-ichiro Abe, Tatsuhiko Sato, Junya Kuroda, S. Manabe, Y. Watanabe, Wang Liao, Kojiro Ito, M. Hashimoto, M. Harada, K. Oikawa, Y. Miyake
The impacts of hydrided and non-hydrided materials near transistors on neutron-induced single event upsets (SEUs) were investigated by simulating monoenergetic neutron irradiations on 65-nm technology bulk static random access memories. The onset energy of the SEUs induced by H ions depends on the shielding capability, i.e., the material and thickness, of components placed in front of transistors when those components do not contain hydrogen atoms. The shielding capability also influences the initial slope observed in the energy-dependence of SEU cross sections. Taking into account the non-hydrided component attached to memory cells used in the simulation, all experimental data measured at each neutron facility were reproduced well using SEU cross sections obtained by simulation. We also find that the effect of components near transistors on neutron-induced soft error rates is not negligible even for irradiation by white neutrons.
{"title":"Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets","authors":"Shin-ichiro Abe, Tatsuhiko Sato, Junya Kuroda, S. Manabe, Y. Watanabe, Wang Liao, Kojiro Ito, M. Hashimoto, M. Harada, K. Oikawa, Y. Miyake","doi":"10.1109/IRPS45951.2020.9128951","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128951","url":null,"abstract":"The impacts of hydrided and non-hydrided materials near transistors on neutron-induced single event upsets (SEUs) were investigated by simulating monoenergetic neutron irradiations on 65-nm technology bulk static random access memories. The onset energy of the SEUs induced by H ions depends on the shielding capability, i.e., the material and thickness, of components placed in front of transistors when those components do not contain hydrogen atoms. The shielding capability also influences the initial slope observed in the energy-dependence of SEU cross sections. Taking into account the non-hydrided component attached to memory cells used in the simulation, all experimental data measured at each neutron facility were reproduced well using SEU cross sections obtained by simulation. We also find that the effect of components near transistors on neutron-induced soft error rates is not negligible even for irradiation by white neutrons.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121189928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128832
J. Locati, V. D. Marca, C. Rivero, A. Régnier, S. Niel, K. Coulié
This paper presents a junction reliability study on a new architecture of high voltage transistor with a double poly gate for Non-Volatile Memory (NVM) Technology. The experiments results are supported by TCAD simulations. The drain-bulk AC stress was performed on the new architecture and compared with the conventional demonstrating an important improvement in terms of reliability, for different bias conditions, taking advantage of its design architecture. Finally, process and design optimizations of the new architecture are presented.
{"title":"AC stress reliability study of a new high voltage transistor for logic memory circuits","authors":"J. Locati, V. D. Marca, C. Rivero, A. Régnier, S. Niel, K. Coulié","doi":"10.1109/IRPS45951.2020.9128832","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128832","url":null,"abstract":"This paper presents a junction reliability study on a new architecture of high voltage transistor with a double poly gate for Non-Volatile Memory (NVM) Technology. The experiments results are supported by TCAD simulations. The drain-bulk AC stress was performed on the new architecture and compared with the conventional demonstrating an important improvement in terms of reliability, for different bias conditions, taking advantage of its design architecture. Finally, process and design optimizations of the new architecture are presented.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121663290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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