A software system architecture for testing multiple part number wafers

R. M. Smyczynski, K. Brennan
{"title":"A software system architecture for testing multiple part number wafers","authors":"R. M. Smyczynski, K. Brennan","doi":"10.1109/VTEST.1991.208147","DOIUrl":null,"url":null,"abstract":"Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208147","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<>
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于测试多零件号晶圆的软件系统架构
测试单个零件号晶圆是当今工业中测试半导体器件的正常模式。然而,随着晶圆越来越大,在同一晶圆上放置不同的设备可能会变得更加经济,从而产生多个零件编号的晶圆。作者描述了一种允许测试这种晶圆的系统架构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A statistical model for fault coverage analysis A software system architecture for testing multiple part number wafers On polynomial-time testable classes of combinational circuits Modeling the effects of imperfect production testing on reconfigurable VLSI chips Circuit-level classification and testability analysis for CMOS faults
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1