{"title":"Circuit-level classification and testability analysis for CMOS faults","authors":"S. Midkiff, S. Bollinger","doi":"10.1109/VTEST.1991.208157","DOIUrl":null,"url":null,"abstract":"The authors examine tests for short and open faults in CMOS circuits considering both IDDQ and logic observation test methods. Short and open faults are classified according to a topological classification that considers the type of fault, fault location, and affected transistor structure. The testability of each fault classification is considered for both optimistic and pessimistic assumptions. Circuit-level simulation is used to illustrate the classification.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
The authors examine tests for short and open faults in CMOS circuits considering both IDDQ and logic observation test methods. Short and open faults are classified according to a topological classification that considers the type of fault, fault location, and affected transistor structure. The testability of each fault classification is considered for both optimistic and pessimistic assumptions. Circuit-level simulation is used to illustrate the classification.<>
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