Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208166
C. Gauthron
Testing ASICs 'at-speed' attempts to improve the test quality by detecting delay-faults. In this paper a methodology to generate at-speed test vectors is described. It is based on the comparison of simulation traces obtained within different timing conditions. The methodology has been automated and successfully used.<>
{"title":"At-speed testing of ASICs","authors":"C. Gauthron","doi":"10.1109/VTEST.1991.208166","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208166","url":null,"abstract":"Testing ASICs 'at-speed' attempts to improve the test quality by detecting delay-faults. In this paper a methodology to generate at-speed test vectors is described. It is based on the comparison of simulation traces obtained within different timing conditions. The methodology has been automated and successfully used.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129934464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208130
K. E. Maadani, J. Geffroy
Presents an original approach to the evaluation of test sequences applied to sequential circuits represented by structured-functional models; the method is based on formal identification of the internal modules of the circuit studied. A prototype software tool has been implemented in PROLOG in order to validate the approach.<>
{"title":"Identification of structured automata for test evaluation","authors":"K. E. Maadani, J. Geffroy","doi":"10.1109/VTEST.1991.208130","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208130","url":null,"abstract":"Presents an original approach to the evaluation of test sequences applied to sequential circuits represented by structured-functional models; the method is based on formal identification of the internal modules of the circuit studied. A prototype software tool has been implemented in PROLOG in order to validate the approach.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124274932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208168
R. Seireg, A. Vacroux
The study of the performance of maximum length and cyclic shift registers has been extended to broader classes of circuits. A new general form for the characteristic equation of the transition probability matrix was deduced which differs from equations obtained earlier.<>
{"title":"Comparison between the dynamic behavior of maximum length and cyclic shift registers","authors":"R. Seireg, A. Vacroux","doi":"10.1109/VTEST.1991.208168","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208168","url":null,"abstract":"The study of the performance of maximum length and cyclic shift registers has been extended to broader classes of circuits. A new general form for the characteristic equation of the transition probability matrix was deduced which differs from equations obtained earlier.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126893837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208164
Jiann-Shiun Yuan, J. Liou, David M. Wu
The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<>
{"title":"Testing the impact of process defects on ECL power-delay performance","authors":"Jiann-Shiun Yuan, J. Liou, David M. Wu","doi":"10.1109/VTEST.1991.208164","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208164","url":null,"abstract":"The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116535421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208124
Harald Gundlach, Bernd K. Koch, K. Müller-Glaser
Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.<>
{"title":"Using target faults to achieve a minimized partial scan path","authors":"Harald Gundlach, Bernd K. Koch, K. Müller-Glaser","doi":"10.1109/VTEST.1991.208124","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208124","url":null,"abstract":"Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208141
W. Wong, J. Liou, Jiann-Shiun Yuan, David M. Wu
A computer-aided design tool for testing MOSFET integrated circuit performance as functions of MOSFET channel length and channel width variations is presented. The numerical model, which is developed based on the Tellegen's theorem and a database that contains the statistical information of MOSFET process parameters, is implemented in SPICE2 circuit simulator. Sensitivity simulation of a MOSFET operational amplifier is carried out to illustrate the usefulness of the present work.<>
{"title":"Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits","authors":"W. Wong, J. Liou, Jiann-Shiun Yuan, David M. Wu","doi":"10.1109/VTEST.1991.208141","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208141","url":null,"abstract":"A computer-aided design tool for testing MOSFET integrated circuit performance as functions of MOSFET channel length and channel width variations is presented. The numerical model, which is developed based on the Tellegen's theorem and a database that contains the statistical information of MOSFET process parameters, is implemented in SPICE2 circuit simulator. Sensitivity simulation of a MOSFET operational amplifier is carried out to illustrate the usefulness of the present work.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127660121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208137
S. F. Oakland
This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<>
{"title":"Combining IEEE Standard 1149.1 with reduced-pin-count component test","authors":"S. F. Oakland","doi":"10.1109/VTEST.1991.208137","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208137","url":null,"abstract":"This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124293917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208125
R. V. Riessen, H. Kerkhoff, Johan Janssen
This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process.<>
{"title":"A design-for-testability expert system for silicon compilers","authors":"R. V. Riessen, H. Kerkhoff, Johan Janssen","doi":"10.1109/VTEST.1991.208125","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208125","url":null,"abstract":"This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134644509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208165
David M. Wu
In this paper, an optimized delay testing technique used in level sensitive scan design (LSSD) circuits is described. Methods of improving delay test effectiveness in four different logic groups of six LSSD test chips are illustrated. Comparison of two delay testing measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level.<>
{"title":"An optimized delay testing technique for LSSD-based VLSI logic circuits","authors":"David M. Wu","doi":"10.1109/VTEST.1991.208165","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208165","url":null,"abstract":"In this paper, an optimized delay testing technique used in level sensitive scan design (LSSD) circuits is described. Methods of improving delay test effectiveness in four different logic groups of six LSSD test chips are illustrated. Comparison of two delay testing measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133285612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208153
P. Lala, F. Busaba, K. Yarlagadda
It is generally agreed now that the major portion of faults in logic system are not of permanent nature. Current testing strategies are incapable of detecting nonpermanent faults. The characteristics of such faults requires that logic circuits be designed in a way so that if there is a fault in the circuit, its effect will be detected during the normal operation of the circuit, i.e. the circuits be self-checking. In this paper the authors propose two rules based on the mode 3 residue coding scheme for designing circuits for online error detection.<>
{"title":"An approach for designing self-checking logic using residue codes","authors":"P. Lala, F. Busaba, K. Yarlagadda","doi":"10.1109/VTEST.1991.208153","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208153","url":null,"abstract":"It is generally agreed now that the major portion of faults in logic system are not of permanent nature. Current testing strategies are incapable of detecting nonpermanent faults. The characteristics of such faults requires that logic circuits be designed in a way so that if there is a fault in the circuit, its effect will be detected during the normal operation of the circuit, i.e. the circuits be self-checking. In this paper the authors propose two rules based on the mode 3 residue coding scheme for designing circuits for online error detection.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133767833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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