Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208166
C. Gauthron
Testing ASICs 'at-speed' attempts to improve the test quality by detecting delay-faults. In this paper a methodology to generate at-speed test vectors is described. It is based on the comparison of simulation traces obtained within different timing conditions. The methodology has been automated and successfully used.<>
{"title":"At-speed testing of ASICs","authors":"C. Gauthron","doi":"10.1109/VTEST.1991.208166","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208166","url":null,"abstract":"Testing ASICs 'at-speed' attempts to improve the test quality by detecting delay-faults. In this paper a methodology to generate at-speed test vectors is described. It is based on the comparison of simulation traces obtained within different timing conditions. The methodology has been automated and successfully used.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129934464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208130
K. E. Maadani, J. Geffroy
Presents an original approach to the evaluation of test sequences applied to sequential circuits represented by structured-functional models; the method is based on formal identification of the internal modules of the circuit studied. A prototype software tool has been implemented in PROLOG in order to validate the approach.<>
{"title":"Identification of structured automata for test evaluation","authors":"K. E. Maadani, J. Geffroy","doi":"10.1109/VTEST.1991.208130","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208130","url":null,"abstract":"Presents an original approach to the evaluation of test sequences applied to sequential circuits represented by structured-functional models; the method is based on formal identification of the internal modules of the circuit studied. A prototype software tool has been implemented in PROLOG in order to validate the approach.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124274932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208168
R. Seireg, A. Vacroux
The study of the performance of maximum length and cyclic shift registers has been extended to broader classes of circuits. A new general form for the characteristic equation of the transition probability matrix was deduced which differs from equations obtained earlier.<>
{"title":"Comparison between the dynamic behavior of maximum length and cyclic shift registers","authors":"R. Seireg, A. Vacroux","doi":"10.1109/VTEST.1991.208168","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208168","url":null,"abstract":"The study of the performance of maximum length and cyclic shift registers has been extended to broader classes of circuits. A new general form for the characteristic equation of the transition probability matrix was deduced which differs from equations obtained earlier.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126893837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208164
Jiann-Shiun Yuan, J. Liou, David M. Wu
The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<>
{"title":"Testing the impact of process defects on ECL power-delay performance","authors":"Jiann-Shiun Yuan, J. Liou, David M. Wu","doi":"10.1109/VTEST.1991.208164","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208164","url":null,"abstract":"The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116535421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208124
Harald Gundlach, Bernd K. Koch, K. Müller-Glaser
Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.<>
{"title":"Using target faults to achieve a minimized partial scan path","authors":"Harald Gundlach, Bernd K. Koch, K. Müller-Glaser","doi":"10.1109/VTEST.1991.208124","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208124","url":null,"abstract":"Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208141
W. Wong, J. Liou, Jiann-Shiun Yuan, David M. Wu
A computer-aided design tool for testing MOSFET integrated circuit performance as functions of MOSFET channel length and channel width variations is presented. The numerical model, which is developed based on the Tellegen's theorem and a database that contains the statistical information of MOSFET process parameters, is implemented in SPICE2 circuit simulator. Sensitivity simulation of a MOSFET operational amplifier is carried out to illustrate the usefulness of the present work.<>
{"title":"Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits","authors":"W. Wong, J. Liou, Jiann-Shiun Yuan, David M. Wu","doi":"10.1109/VTEST.1991.208141","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208141","url":null,"abstract":"A computer-aided design tool for testing MOSFET integrated circuit performance as functions of MOSFET channel length and channel width variations is presented. The numerical model, which is developed based on the Tellegen's theorem and a database that contains the statistical information of MOSFET process parameters, is implemented in SPICE2 circuit simulator. Sensitivity simulation of a MOSFET operational amplifier is carried out to illustrate the usefulness of the present work.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127660121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208149
B. Ciciani
An innovative method for the 'apparent' yield evaluation is presented. By this method it is possible to evaluate the quality of the manufacturing process and the expected fraction of truly good chips at the end of the testing and reconfiguration phase. It permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy. It is easy to use and permits the predictability of the approximation level of the yield values.<>
{"title":"Modeling the effects of imperfect production testing on reconfigurable VLSI chips","authors":"B. Ciciani","doi":"10.1109/VTEST.1991.208149","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208149","url":null,"abstract":"An innovative method for the 'apparent' yield evaluation is presented. By this method it is possible to evaluate the quality of the manufacturing process and the expected fraction of truly good chips at the end of the testing and reconfiguration phase. It permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy. It is easy to use and permits the predictability of the approximation level of the yield values.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115202657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208151
D. Sweetman
The test and guardband philosophy is essential in the manufacturing of integrated circuits. The philosophy integrates the general rules for test sequences, hardware, and software. The data sheet and philosophy determine the values and methodology for parameter and functional tests. Guardbanding is the off-setting of a test parameter, condition, or attribute acceptance level from the specified value. Variability in equipment and device performance necessitate machine guardbands. Device and test program guardbands improve test productivity. Changing the applied, measured, or external conditions from those specified implements the guardbands for attribute testing. The author addresses the use of guardbands for an MOS VLSI EEPROM, i.e. a nonvolatile reprogrammable memory.<>
{"title":"Guardbanding VLSI EEPROM test programs","authors":"D. Sweetman","doi":"10.1109/VTEST.1991.208151","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208151","url":null,"abstract":"The test and guardband philosophy is essential in the manufacturing of integrated circuits. The philosophy integrates the general rules for test sequences, hardware, and software. The data sheet and philosophy determine the values and methodology for parameter and functional tests. Guardbanding is the off-setting of a test parameter, condition, or attribute acceptance level from the specified value. Variability in equipment and device performance necessitate machine guardbands. Device and test program guardbands improve test productivity. Changing the applied, measured, or external conditions from those specified implements the guardbands for attribute testing. The author addresses the use of guardbands for an MOS VLSI EEPROM, i.e. a nonvolatile reprogrammable memory.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115634900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208147
R. M. Smyczynski, K. Brennan
Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<>
{"title":"A software system architecture for testing multiple part number wafers","authors":"R. M. Smyczynski, K. Brennan","doi":"10.1109/VTEST.1991.208147","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208147","url":null,"abstract":"Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-04-15DOI: 10.1109/VTEST.1991.208148
R. Rajsuman, A. Jayasumana, Y. Malaiya, Juney Park
The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.<>
{"title":"An analysis and testing of operation induced faults in MOS VLSI","authors":"R. Rajsuman, A. Jayasumana, Y. Malaiya, Juney Park","doi":"10.1109/VTEST.1991.208148","DOIUrl":"https://doi.org/10.1109/VTEST.1991.208148","url":null,"abstract":"The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122834650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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