Minimum parasitic resistance for ultra-thin SOI MOSFET with high-permittivity gate insulator performed by lateral contact structure

Abstract

Since the interconnect capacitance almost maintains the same level even with shrinking device dimension, high current drive of a transistor is required for ultra-high speed operation. Although the ultra-thin SOI MOSFET is a promising candidate for ultra-small devices, its enormous parasitic resistance is a significant problem. The reduction of the parasitic resistance is a key issue in achieving high-performance ultra-thin SOI devices. In this study, a lateral contact structure, unique to SOI devices, with ultra-low contact resistance, is proposed for realizing ultimate low parasitic resistance.