A. Yoshino, K. Kumagai, N. Hamatake, T. Tatsumi, H. Onishi, S. Kurosawa, K. Okumura
High speed performances of CMOS/SIMOX circuits have been demonstrated using the low dose SIMOX substrate in spite of the thin (80nm) buried oxide layer. The following two factors have been pointed out to understand the results: (i) the depletion layer which spreads underneath the buried oxide (BOX) layer, and (ii) the Vth-lowering in the PMOS transistor due to the negative back bias (VGB=-VDD) effect. However, the correlations between the high speed performance and these two factors have not been shown in detail. In this paper, we clarify the nature of the high speed performance of the fully depleted mode ultrathin CMOS/SIMOX gates fabricated on the low dose SIMOX substrate on the basis of our experimental results.
{"title":"High speed performance of 0.35 /spl mu/m CMOS gates fabricated on low dose SIMOX substrates with/without N-well underneath the buried oxide layer","authors":"A. Yoshino, K. Kumagai, N. Hamatake, T. Tatsumi, H. Onishi, S. Kurosawa, K. Okumura","doi":"10.1109/SOI.1995.526437","DOIUrl":"https://doi.org/10.1109/SOI.1995.526437","url":null,"abstract":"High speed performances of CMOS/SIMOX circuits have been demonstrated using the low dose SIMOX substrate in spite of the thin (80nm) buried oxide layer. The following two factors have been pointed out to understand the results: (i) the depletion layer which spreads underneath the buried oxide (BOX) layer, and (ii) the Vth-lowering in the PMOS transistor due to the negative back bias (VGB=-VDD) effect. However, the correlations between the high speed performance and these two factors have not been shown in detail. In this paper, we clarify the nature of the high speed performance of the fully depleted mode ultrathin CMOS/SIMOX gates fabricated on the low dose SIMOX substrate on the basis of our experimental results.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125878877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
While SOI wafer manufacturing processes such as SIMOX and BESOI have been developed, it remains a challenge to produce SOI wafers with extremely thin top silicon layers that are uniform in thickness, low in defects, high in crystalline quality, and compatible to bulk silicon in electrical performance. These stringent requirements on SOI wafers have stimulated a parallel effort to develop characterization techniques for starting SOI wafer qualification, as conventional characterization techniques often prove to be inadequate as a result of complications arising from the presence of the buried oxide layer in SOI. New methods therefore have emerged to answer the needs. Here we report the use of optical second harmonic generation (SHG) method for the characterization of SOI wafer quality. This technique is non-destructive, real time, very sensitive and versatile. It can be used to address a number of SOI wafer issues such as silicon film uniformity, wafer bonding induced mechanical stress, dopant and defect density in the thin film, and buried oxide layer interfacial quality. Applying this method to the investigation of BESOI and SIMOX wafers, we have observed distinctive SHG signals and signal changes as the wafers are subjected to different processing conditions. These results indicate that the quality of the SOI wafers can in fact be probed effectively using the SHG technique.
{"title":"SOI material characterization using optical second harmonic generation","authors":"Y. Gu, T. Vu, G. Li","doi":"10.1109/SOI.1995.526477","DOIUrl":"https://doi.org/10.1109/SOI.1995.526477","url":null,"abstract":"While SOI wafer manufacturing processes such as SIMOX and BESOI have been developed, it remains a challenge to produce SOI wafers with extremely thin top silicon layers that are uniform in thickness, low in defects, high in crystalline quality, and compatible to bulk silicon in electrical performance. These stringent requirements on SOI wafers have stimulated a parallel effort to develop characterization techniques for starting SOI wafer qualification, as conventional characterization techniques often prove to be inadequate as a result of complications arising from the presence of the buried oxide layer in SOI. New methods therefore have emerged to answer the needs. Here we report the use of optical second harmonic generation (SHG) method for the characterization of SOI wafer quality. This technique is non-destructive, real time, very sensitive and versatile. It can be used to address a number of SOI wafer issues such as silicon film uniformity, wafer bonding induced mechanical stress, dopant and defect density in the thin film, and buried oxide layer interfacial quality. Applying this method to the investigation of BESOI and SIMOX wafers, we have observed distinctive SHG signals and signal changes as the wafers are subjected to different processing conditions. These results indicate that the quality of the SOI wafers can in fact be probed effectively using the SHG technique.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The buried oxide (BOX) of SIMOX structures exhibits stronger electron trapping than thermally grown SiO/sub 2/ films and contains photo-active centers which can be positively charged. The electron traps with large cross section and the photo-active centers were ascribed to small Si clusters whose density is related to the oxygen implantation mode and subsequent processing. This work shows that the photo-active defects are of the same type in all the BOX layers but their size and density depend, among others, on the implantation energy, oxygen dose, and annealing conditions. If sufficient excess silicon is present in the BOX, then, in addition to amorphous Si clusters, crystalline Si islands form as well. The formation and stability of both types of Si inclusions are related to the confined nature of the BOX layer which, in turn, is affected by the Si substrate.
{"title":"Energy levels of electrons trapped in buried oxide of SIMOX structures","authors":"V. Afanas'ev, A. Revesz, W. Jenkins, H. Hughes","doi":"10.1109/SOI.1995.526481","DOIUrl":"https://doi.org/10.1109/SOI.1995.526481","url":null,"abstract":"The buried oxide (BOX) of SIMOX structures exhibits stronger electron trapping than thermally grown SiO/sub 2/ films and contains photo-active centers which can be positively charged. The electron traps with large cross section and the photo-active centers were ascribed to small Si clusters whose density is related to the oxygen implantation mode and subsequent processing. This work shows that the photo-active defects are of the same type in all the BOX layers but their size and density depend, among others, on the implantation energy, oxygen dose, and annealing conditions. If sufficient excess silicon is present in the BOX, then, in addition to amorphous Si clusters, crystalline Si islands form as well. The formation and stability of both types of Si inclusions are related to the confined nature of the BOX layer which, in turn, is affected by the Si substrate.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116741029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work investigates the feasibility of realisation of SOI CMOS Operational Transconductance Amplifiers (OTA) operating up to 1 GHz. In contrast to a previously published microwave wideband amplifier driving low ohmic resistive line termination, OTAs for Switched-Capacitor (SC) applications need a high impedance and capacitive output node. In addition applications such as sigma-delta converters require fast OTAs. In order to reduce the settling time, the transfer function should also include a minimal amount of poles and zeros. Consequently in spite of its low voltage gain, this single-stage OTA could be of interest for high-frequency applications.
{"title":"A 1-GHz operational transconductance amplifier in SOI technology","authors":"J. Eggermont, D. Flandre, R. Gillon, J. Colinge","doi":"10.1109/SOI.1995.526493","DOIUrl":"https://doi.org/10.1109/SOI.1995.526493","url":null,"abstract":"This work investigates the feasibility of realisation of SOI CMOS Operational Transconductance Amplifiers (OTA) operating up to 1 GHz. In contrast to a previously published microwave wideband amplifier driving low ohmic resistive line termination, OTAs for Switched-Capacitor (SC) applications need a high impedance and capacitive output node. In addition applications such as sigma-delta converters require fast OTAs. In order to reduce the settling time, the transfer function should also include a minimal amount of poles and zeros. Consequently in spite of its low voltage gain, this single-stage OTA could be of interest for high-frequency applications.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124184744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a convenient and direct method for extracting thermal impedance for fully-depleted SOI MOSFETs. The results are consistent with thermal resistance calculations using a physical model. Demonstration of the use of a Thermal Impedance Pre-Processor applied to an electrothermal circuit model in the simulator Saber to predict thermal transient response is also provided along with measurement data.
{"title":"Extraction of thermal resistance for fully-depleted SOI MOSFETs","authors":"T. Lee, R. Fox","doi":"10.1109/SOI.1995.526469","DOIUrl":"https://doi.org/10.1109/SOI.1995.526469","url":null,"abstract":"This paper presents a convenient and direct method for extracting thermal impedance for fully-depleted SOI MOSFETs. The results are consistent with thermal resistance calculations using a physical model. Demonstration of the use of a Thermal Impedance Pre-Processor applied to an electrothermal circuit model in the simulator Saber to predict thermal transient response is also provided along with measurement data.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132233571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have demonstrated a manufacturable final CMP based process to recover the roughness of as-prepared SOI wafers. The roughness achievable is comparable to prime Si bulk wafers and in keeping with Si wafer requirements for ULSI. Concomitant to the process is some TTV degradation. Our process has been tuned to minimize this degradation and to keep it consistent with CMOS/SOI requirements on TTV.
{"title":"Final polish for SOI wafers-surface roughness and TTV degradation","authors":"G. Pfeiffer, S. Fetheroff, S. S. Iyer","doi":"10.1109/SOI.1995.526515","DOIUrl":"https://doi.org/10.1109/SOI.1995.526515","url":null,"abstract":"We have demonstrated a manufacturable final CMP based process to recover the roughness of as-prepared SOI wafers. The roughness achievable is comparable to prime Si bulk wafers and in keeping with Si wafer requirements for ULSI. Concomitant to the process is some TTV degradation. Our process has been tuned to minimize this degradation and to keep it consistent with CMOS/SOI requirements on TTV.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114791891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This abstract describes one of the first attempts to apply high-field electrical testing to obtain BOX metrological information previously obtainable only via traditional physical analysis. The advantages of electrical analysis are several: it has a relatively low turn-around time, and provides high-volume statistical information about many BOX characteristics.
{"title":"Use of high-field electrical testing for SIMOX BOX metrology","authors":"J. Yoon, J. Nee, J. Yap, J. E. Chung","doi":"10.1109/SOI.1995.526502","DOIUrl":"https://doi.org/10.1109/SOI.1995.526502","url":null,"abstract":"This abstract describes one of the first attempts to apply high-field electrical testing to obtain BOX metrological information previously obtainable only via traditional physical analysis. The advantages of electrical analysis are several: it has a relatively low turn-around time, and provides high-volume statistical information about many BOX characteristics.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129356782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Azuma, A. Kishi, M. Tanigawa, S. Kaneko, T. Naka, A. Ishihawa, K. Iguchi, K. Sakiyama
Fully-depleted, ultra-thin SIMOX/CMOS is a suitable technology to achieve low voltage and high speed application because of its capability of low Vth operation. However, large resistivity of diffusion area is an issue. In this paper,a thin salicidation layer was adopted to decrease the sheet resistivity of the ultra-thin SIMOX layer. Good transistor characteristics with sheet resistivity less than one tenth of the non-silicided diffusion resistivity were achieved, and no degradation of the transistor characteristics was observed.
{"title":"Application of Ti salicide process on ultra-thin SIMOX wafer","authors":"K. Azuma, A. Kishi, M. Tanigawa, S. Kaneko, T. Naka, A. Ishihawa, K. Iguchi, K. Sakiyama","doi":"10.1109/SOI.1995.526445","DOIUrl":"https://doi.org/10.1109/SOI.1995.526445","url":null,"abstract":"Fully-depleted, ultra-thin SIMOX/CMOS is a suitable technology to achieve low voltage and high speed application because of its capability of low Vth operation. However, large resistivity of diffusion area is an issue. In this paper,a thin salicidation layer was adopted to decrease the sheet resistivity of the ultra-thin SIMOX layer. Good transistor characteristics with sheet resistivity less than one tenth of the non-silicided diffusion resistivity were achieved, and no degradation of the transistor characteristics was observed.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127273468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R.A. Johnson, C.E. Chang, P. de la Houssaye, G. Garcia, I. Lagnado, P. Asbeck
We report the microwave characteristics and modeling of thin-film silicon-on-sapphire n- and p-channel MOS transistors with high f/sub max/, and low F/sub min/. N-channel and p-channel MOSFETs were fabricated with optically defined low resistance T-gates and found to have f/sub max/ values above 60 GHz and 40 GHz, respectively. The minimum noise figure, F/sub min/ was below 1 dB at 2 GHz for both devices. Both the f/sub max/ and F/sub min/ values are the best reported to date for silicon MOSFETs. A small signal model, similar to that used for MESFETs, is used here to model the devices, extract the small signal parameters and correlate the device structure with the measured performance.
{"title":"Microwave characteristics of high f/sub max/ low noise thin film silicon-on-sapphire MOSFETs","authors":"R.A. Johnson, C.E. Chang, P. de la Houssaye, G. Garcia, I. Lagnado, P. Asbeck","doi":"10.1109/SOI.1995.526439","DOIUrl":"https://doi.org/10.1109/SOI.1995.526439","url":null,"abstract":"We report the microwave characteristics and modeling of thin-film silicon-on-sapphire n- and p-channel MOS transistors with high f/sub max/, and low F/sub min/. N-channel and p-channel MOSFETs were fabricated with optically defined low resistance T-gates and found to have f/sub max/ values above 60 GHz and 40 GHz, respectively. The minimum noise figure, F/sub min/ was below 1 dB at 2 GHz for both devices. Both the f/sub max/ and F/sub min/ values are the best reported to date for silicon MOSFETs. A small signal model, similar to that used for MESFETs, is used here to model the devices, extract the small signal parameters and correlate the device structure with the measured performance.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"448 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131714562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Lawrence, D. Ioannou, R.E. Stahibush, H. Hughes
Photocurrent measurements have been performed on internal thermal oxide (ITOX) buried oxide (BOX) SIMOX structures. After electron injection, from a 5eV mercury light source, the net electron trapping per area for the ITOX structure was found to be larger than that of a control SIMOX structure. This increase has been attributed to the ITOX's process influence on the formation of the ITOX/BOX oxide.
{"title":"Photocurrent measurements of electron traps on ITOX processed SIMOX structures","authors":"R. Lawrence, D. Ioannou, R.E. Stahibush, H. Hughes","doi":"10.1109/SOI.1995.526503","DOIUrl":"https://doi.org/10.1109/SOI.1995.526503","url":null,"abstract":"Photocurrent measurements have been performed on internal thermal oxide (ITOX) buried oxide (BOX) SIMOX structures. After electron injection, from a 5eV mercury light source, the net electron trapping per area for the ITOX structure was found to be larger than that of a control SIMOX structure. This increase has been attributed to the ITOX's process influence on the formation of the ITOX/BOX oxide.","PeriodicalId":149490,"journal":{"name":"1995 IEEE International SOI Conference Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126517105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：