TCAD-prototyping with new accurate worst-case definition for a 0.2 micron CMOS-ASIC process

Abstract

An industrial statistical worst case modeling process for 0.2 /spl mu/m CMOS is presented. It is based on new TCAD-prototyping with efficient correlation analysis for CMOS performance goals under process variability. Since the manufacturing process undergoes ongoing improvement, well-calibrated TCAD is primary tool to construct realistic performance corner models. A robust TCAD calibration method is one of the keys to achieving accurate prediction. Statistically least conservative "worst case" conditions are newly identified, which state that 99.7% of device performance is contained between the FF (fast fast) and SS (slow slow) worst corners. This reduces the design guardband by 10% compared with conventional worst case approaches.