Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773186
J. Vázquez-González, G. E. Flores-Verdad
This paper demonstrates how response surface methods can be applied in the fault diagnosis of analog integrated circuits. The method involves experimental design and principal components analysis to identify which parameters appear to be important and which are irrelevant, so that they can be fixed at some reasonable value and omitted from further considerations. When the principal parameters have been chosen, regression techniques are used to obtain models that approximate the performance of the analog integrated circuit. The constructed models have enough information to find the circuit fault when it is tested.
{"title":"Fault diagnosis of analog integrated circuits using response surface methods","authors":"J. Vázquez-González, G. E. Flores-Verdad","doi":"10.1109/IWSTM.1999.773186","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773186","url":null,"abstract":"This paper demonstrates how response surface methods can be applied in the fault diagnosis of analog integrated circuits. The method involves experimental design and principal components analysis to identify which parameters appear to be important and which are irrelevant, so that they can be fixed at some reasonable value and omitted from further considerations. When the principal parameters have been chosen, regression techniques are used to obtain models that approximate the performance of the analog integrated circuit. The constructed models have enough information to find the circuit fault when it is tested.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773195
V. Nilsen, A. J. Walton, J. Donnelly, G. Horsburgh, R. Childs
This paper describes a methodology for using TCAD as an aid to process transfer. The methodology is based on the use of a semi-automated system developed to reduce the effort required by the user in developing the TCAD code, thereby reducing the time taken to implement a process transfer. The issues involved in process transfer are considered, as is the role that TCAD can play in the procedure. The operation of the system is outlined and an example of its application is used to indicate its potential.
{"title":"Implementation of a TCAD based system to aid process transfer","authors":"V. Nilsen, A. J. Walton, J. Donnelly, G. Horsburgh, R. Childs","doi":"10.1109/IWSTM.1999.773195","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773195","url":null,"abstract":"This paper describes a methodology for using TCAD as an aid to process transfer. The methodology is based on the use of a semi-automated system developed to reduce the effort required by the user in developing the TCAD code, thereby reducing the time taken to implement a process transfer. The issues involved in process transfer are considered, as is the role that TCAD can play in the procedure. The operation of the system is outlined and an example of its application is used to indicate its potential.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128769524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773197
A. Goda, A. Misaka, S. Odanaka
Optical lithographic processing continues to be the mainstream technology for /spl les/0.18 /spl mu/m generations with the development of wavelength resolution (KrF, ArF), resolution enhancement technology (RET) such as off-axis illumination and phase shifting masks. The ULSI manufacturing process faces CD variation as a new issue (Pforr et al., 1995). Two major factors of CD variation are process variation and the optical proximity effect, which depends on the pattern layout. Hence, statistical gate CD control considering the CD variation caused by these two factors is a key issue in the ULSI manufacturing process. In this paper, we describe the RSF with variable coefficients for CD variation analysis, including mask bias OPC (optical proximity correction). The RSF with variable coefficients to lens conditions NA and /spl sigma/ is newly developed, indicating the nonlinear dependence of CD on the focus position. This approach allows CD variation analysis including mask bias OPC, even when the line width comes close to the stepper wavelength.
随着波长分辨率(KrF、ArF)、离轴照明和移相掩模等分辨率增强技术(RET)的发展，光学光刻工艺继续成为/spl les/0.18 /spl mu/m世代的主流技术。ULSI制造工艺面临的CD变化是一个新问题(Pforr et al.， 1995)。CD变化的两个主要因素是工艺变化和光学邻近效应，这取决于图案布局。因此，考虑到这两个因素引起的CD变化的统计门CD控制是ULSI制造过程中的关键问题。在本文中，我们描述了用于CD变化分析的可变系数RSF，包括掩模偏置OPC(光学接近校正)。新提出了随透镜条件NA和/spl σ /变系数的RSF，表明CD对焦点位置的非线性依赖。这种方法允许包括掩模偏置OPC在内的CD变化分析，即使线宽接近步进波长。
{"title":"Impact of RSF with variable coefficients for CD variation analysis including OPC","authors":"A. Goda, A. Misaka, S. Odanaka","doi":"10.1109/IWSTM.1999.773197","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773197","url":null,"abstract":"Optical lithographic processing continues to be the mainstream technology for /spl les/0.18 /spl mu/m generations with the development of wavelength resolution (KrF, ArF), resolution enhancement technology (RET) such as off-axis illumination and phase shifting masks. The ULSI manufacturing process faces CD variation as a new issue (Pforr et al., 1995). Two major factors of CD variation are process variation and the optical proximity effect, which depends on the pattern layout. Hence, statistical gate CD control considering the CD variation caused by these two factors is a key issue in the ULSI manufacturing process. In this paper, we describe the RSF with variable coefficients for CD variation analysis, including mask bias OPC (optical proximity correction). The RSF with variable coefficients to lens conditions NA and /spl sigma/ is newly developed, indicating the nonlinear dependence of CD on the focus position. This approach allows CD variation analysis including mask bias OPC, even when the line width comes close to the stepper wavelength.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115007272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773185
S. Zanella, A. Nardi, M. Quarantelli, A. Neviani, C. Guardiani
In this work, we analyze the impact of local process variations on the clock skew of VLSI circuits designed in deep sub-micron technologies. As the size of active repeaters decreases, the utilization of dense buffering schemes, up to complete replacement of metal wiring with active devices, has been proposed in order to realize efficient and noise-immune clock distribution networks. However, local variance of MOSFET electrical parameters, such as V/sub T/ and I/sub DSS/, increases with scaling of device dimensions, thus causing large intra-die variability of the timing properties of clock buffers. As a consequence, we expect local mismatch to be a significant source of clock skew in deep sub-micron technologies. In order to accurately verify this assumption, we applied advanced statistical simulation techniques and accurate mismatch characterization data to the statistical simulation of relatively small clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the mismatch effect confirmed that it is necessary to account for local device variations in the design and sizing of the clock distribution network.
{"title":"Analysis of the impact of intra-die variance on clock skew","authors":"S. Zanella, A. Nardi, M. Quarantelli, A. Neviani, C. Guardiani","doi":"10.1109/IWSTM.1999.773185","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773185","url":null,"abstract":"In this work, we analyze the impact of local process variations on the clock skew of VLSI circuits designed in deep sub-micron technologies. As the size of active repeaters decreases, the utilization of dense buffering schemes, up to complete replacement of metal wiring with active devices, has been proposed in order to realize efficient and noise-immune clock distribution networks. However, local variance of MOSFET electrical parameters, such as V/sub T/ and I/sub DSS/, increases with scaling of device dimensions, thus causing large intra-die variability of the timing properties of clock buffers. As a consequence, we expect local mismatch to be a significant source of clock skew in deep sub-micron technologies. In order to accurately verify this assumption, we applied advanced statistical simulation techniques and accurate mismatch characterization data to the statistical simulation of relatively small clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the mismatch effect confirmed that it is necessary to account for local device variations in the design and sizing of the clock distribution network.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121574224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773189
K. Kato, A. Ueki, T. Kaga
This paper discusses high S/N (signal-to-noise) ratio inspection of sub-quarter micrometer oxide CMP defects, e.g. surface particles, micro-scratches, and pits, using a laser scattering inspection tool. For high S/N inspection, (1) reduction of noise signals from embedded particles, and (2) improvement in sensitivity are the objectives. Optimal selection of the incident-light angle of the laser tool, polarization of the scattered light, and optimized sample structures enable us to achieve the objectives. By applying the new high S/N inspection method, a new insight has been found, i.e. total defect count is in proportion to defect size (threshold value) with the rule of power of -6, which is much larger than the conventional value of -2. Among the killer defects, pits mainly increase very rapidly with the decrease in size. The slope is approximately -7 in the log(count)-log(size) plot.
{"title":"High signal-to-noise ratio inspection of sub-quarter micrometer oxide CMP defects by using laser scattering inspection tool","authors":"K. Kato, A. Ueki, T. Kaga","doi":"10.1109/IWSTM.1999.773189","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773189","url":null,"abstract":"This paper discusses high S/N (signal-to-noise) ratio inspection of sub-quarter micrometer oxide CMP defects, e.g. surface particles, micro-scratches, and pits, using a laser scattering inspection tool. For high S/N inspection, (1) reduction of noise signals from embedded particles, and (2) improvement in sensitivity are the objectives. Optimal selection of the incident-light angle of the laser tool, polarization of the scattered light, and optimized sample structures enable us to achieve the objectives. By applying the new high S/N inspection method, a new insight has been found, i.e. total defect count is in proportion to defect size (threshold value) with the rule of power of -6, which is much larger than the conventional value of -2. Among the killer defects, pits mainly increase very rapidly with the decrease in size. The slope is approximately -7 in the log(count)-log(size) plot.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123935364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773194
V. Senez, A. Tixier, T. Hoffmann
The models used for process simulation must be carefully calibrated in order to insure correct prediction of the topography and doping/stress profiles of microelectronic devices. With the current miniaturization of these devices, the requirements for the accuracy of the simulated results become greater, placing more constraints on the calibration methodology. This is particularly the case for the silicon oxidation model, which is involved in numerous fundamental steps of an industrial process. In this work, using the response surface methodology, a viscoelastic oxidation model has been calibrated on a wide range of process conditions which has allowed the optimization of LOCOS type isolation structures for a 0.35 /spl mu/m CMOS technology.
{"title":"Calibration of a 2D numerical model for the optimization of LOCOS type isolations by response surface methodology","authors":"V. Senez, A. Tixier, T. Hoffmann","doi":"10.1109/IWSTM.1999.773194","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773194","url":null,"abstract":"The models used for process simulation must be carefully calibrated in order to insure correct prediction of the topography and doping/stress profiles of microelectronic devices. With the current miniaturization of these devices, the requirements for the accuracy of the simulated results become greater, placing more constraints on the calibration methodology. This is particularly the case for the silicon oxidation model, which is involved in numerous fundamental steps of an industrial process. In this work, using the response surface methodology, a viscoelastic oxidation model has been calibrated on a wide range of process conditions which has allowed the optimization of LOCOS type isolation structures for a 0.35 /spl mu/m CMOS technology.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127448306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773184
M. Orshansky, C. Spanos, C. Hu
In this paper, circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into the deep sub-micron regime, the interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 /spl mu/m CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.
{"title":"Circuit performance variability decomposition","authors":"M. Orshansky, C. Spanos, C. Hu","doi":"10.1109/IWSTM.1999.773184","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773184","url":null,"abstract":"In this paper, circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into the deep sub-micron regime, the interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 /spl mu/m CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114829680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773183
S. Sauter, D. Cousinard, R. Thewes, D. Schmitt-Landsiedel, W. Weber
Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions at chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42 ps for a 0.25 /spl mu/m process and a metal-3 H-clock tree.
{"title":"Clock skew determination from parameter variations at chip and wafer level","authors":"S. Sauter, D. Cousinard, R. Thewes, D. Schmitt-Landsiedel, W. Weber","doi":"10.1109/IWSTM.1999.773183","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773183","url":null,"abstract":"Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions at chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42 ps for a 0.25 /spl mu/m process and a metal-3 H-clock tree.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126871305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773187
K. Imai, T. Kaga
With the increase in importance of lithography processes in the sub-0.25 /spl mu/m era, it is becoming critical to extract repeated defects resulting from mask-related defects or from the lithography margin. In this paper, a new filtering method to extract repeated defects (FIMER) is proposed. It is shown by simulation that FIMER is superior to the conventional windowing method in extracting the repeated defects. For the simulation studies taken up in this paper, the repeated defects are extracted by FIMER with error of less than 5%.
{"title":"A new filtering method to extract repeated defects (FIMER) [lithography]","authors":"K. Imai, T. Kaga","doi":"10.1109/IWSTM.1999.773187","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773187","url":null,"abstract":"With the increase in importance of lithography processes in the sub-0.25 /spl mu/m era, it is becoming critical to extract repeated defects resulting from mask-related defects or from the lithography margin. In this paper, a new filtering method to extract repeated defects (FIMER) is proposed. It is shown by simulation that FIMER is superior to the conventional windowing method in extracting the repeated defects. For the simulation studies taken up in this paper, the repeated defects are extracted by FIMER with error of less than 5%.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122684190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773188
H. Kikuchi, N. Nishio
This paper presents a method for quantitative defect analysis and yield forecast by using a new kill rate from line monitoring data. This kill rate is based on the average of kill rates from dice with the same numbers of the same type of defect occurrences on a die. A simulation study indicated that this new method is superior to conventional methods for multiple defect occurrences on a die.
{"title":"A method of quantitative defect analysis and yield forecast by an advanced kill rate from line monitoring data","authors":"H. Kikuchi, N. Nishio","doi":"10.1109/IWSTM.1999.773188","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773188","url":null,"abstract":"This paper presents a method for quantitative defect analysis and yield forecast by using a new kill rate from line monitoring data. This kill rate is based on the average of kill rates from dice with the same numbers of the same type of defect occurrences on a die. A simulation study indicated that this new method is superior to conventional methods for multiple defect occurrences on a die.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117239456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：