Electrical/thermal co-design and co-simulation, from chip, package, board to system

Abstract

It has been well known for years that as the critical feature size within a chip keeps shrinking, design and optimization among power, heat and performance would become even challenging. On one hand, the electrical functionalities of the devices are closely coupled with temperature and power distributions. On the other hand, the devices within the chip are not totally isolated and confined - the connection and interaction with the environments such as the package, board, and enclosure cannot be ignored especially from the heat transport perspective. Simulation tools in electronic design automation have to satisfy the requirement of electrical/thermal co-simulation for advanced electronic systems having a wide range of critical sizes, and provide efficient approaches with accurate data for design optimization. This is the main purpose of this paper, and we introduce a portfolio of tools to facilitate electrical/thermal co-simulation from chip, package, board to system.