Effects of fault tolerance on the reliability of memory array supports

Abstract

For future-generation large-scale computers, memory reliability is independent of the memory chip failures due to low failure rates and fault-tolerant techniques. When failures do occur, they are masked, using such techniques as single error correction (SEC), page deallocation, and array chip sparing. The two remaining sources of failures are card(s) and logic support modules. This paper describes a method to minimize the effects of logic fails by using logic redundancy.<>