Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199965
Y.-N. Shen, F. Lombardi
Presents various new approaches for concurrent built-in self-test (CBIST). These new approaches have a low latency in fault detection. Two approaches are proposed. The first approach is applicable to combinational logic circuits which can be designed using iterative logic arrays (ILAs). Two methods namely the HIT-COMPRESS and HIT-IDENTICAL, are discussed. These methods employ different hardware structures to accomplish on-line detection. The second approach is applicable to sequential circuits. Two implementations are presented. The first implementation is based on a ring counter, while the second implementation utilizes a parity tree. The principles of operation of these approaches have been fully analyzed and it is proved that fault latency is considerably less than in previous approaches. Hardware overhead issues are also analyzed.<>
{"title":"Concurrent built-in self-test with reduced fault latency","authors":"Y.-N. Shen, F. Lombardi","doi":"10.1109/DFTVS.1991.199965","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199965","url":null,"abstract":"Presents various new approaches for concurrent built-in self-test (CBIST). These new approaches have a low latency in fault detection. Two approaches are proposed. The first approach is applicable to combinational logic circuits which can be designed using iterative logic arrays (ILAs). Two methods namely the HIT-COMPRESS and HIT-IDENTICAL, are discussed. These methods employ different hardware structures to accomplish on-line detection. The second approach is applicable to sequential circuits. Two implementations are presented. The first implementation is based on a ring counter, while the second implementation utilizes a parity tree. The principles of operation of these approaches have been fully analyzed and it is proved that fault latency is considerably less than in previous approaches. Hardware overhead issues are also analyzed.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125202197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199954
F. J. Aichelmann
For future-generation large-scale computers, memory reliability is independent of the memory chip failures due to low failure rates and fault-tolerant techniques. When failures do occur, they are masked, using such techniques as single error correction (SEC), page deallocation, and array chip sparing. The two remaining sources of failures are card(s) and logic support modules. This paper describes a method to minimize the effects of logic fails by using logic redundancy.<>
{"title":"Effects of fault tolerance on the reliability of memory array supports","authors":"F. J. Aichelmann","doi":"10.1109/DFTVS.1991.199954","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199954","url":null,"abstract":"For future-generation large-scale computers, memory reliability is independent of the memory chip failures due to low failure rates and fault-tolerant techniques. When failures do occur, they are masked, using such techniques as single error correction (SEC), page deallocation, and array chip sparing. The two remaining sources of failures are card(s) and logic support modules. This paper describes a method to minimize the effects of logic fails by using logic redundancy.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114555160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199956
N. Lopez-Benitez, M. Chean
One objective in the design of VLSI/WSI fault-tolerant processor arrays (FTPA), is to increase the probability of successful reconfiguration in the presence of one or more faults given that a fault has occurred (survivability). This paper reports a comparison of FUSS (Full-Use-of-Suitable-Spares), a recently proposed reconfiguration scheme, with other two well reconfiguration schemes. The results reported were obtained using MGRE (Model Generator and Reliability Evaluator). The models generated, already take into account the survivability rate of each reconfiguration scheme. This factor is obtained via simulation or whenever possible analytical expressions are derived.<>
VLSI/WSI容错处理器阵列(FTPA)设计的一个目标是，在存在一个或多个故障的情况下，增加成功重新配置的概率(生存性)。本文报道了最近提出的一种重新配置方案FUSS (full use -of- suitesares)与其他两种井重新配置方案的比较。报告的结果是通过MGRE(模型生成器和可靠性评估器)获得的。生成的模型已经考虑了每种重构方案的存活率。这个因子是通过模拟得到的，或者在可能的情况下推导出解析表达式。
{"title":"Reliability evaluation of FUSS and other reconfiguration schemes","authors":"N. Lopez-Benitez, M. Chean","doi":"10.1109/DFTVS.1991.199956","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199956","url":null,"abstract":"One objective in the design of VLSI/WSI fault-tolerant processor arrays (FTPA), is to increase the probability of successful reconfiguration in the presence of one or more faults given that a fault has occurred (survivability). This paper reports a comparison of FUSS (Full-Use-of-Suitable-Spares), a recently proposed reconfiguration scheme, with other two well reconfiguration schemes. The results reported were obtained using MGRE (Model Generator and Reliability Evaluator). The models generated, already take into account the survivability rate of each reconfiguration scheme. This factor is obtained via simulation or whenever possible analytical expressions are derived.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114846138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199942
A. Andreou
Future large scale analog computational systems will have to cope with manufacturing defects and mismatch in individual components. The author argues that current-mode design techniques, and in particular minimal designs at the transistor level are consistent with future manufacturing requirements for wafer scale analog systems.<>
{"title":"Current-mode techniques for analog VLSI: technology and defect tolerance issues","authors":"A. Andreou","doi":"10.1109/DFTVS.1991.199942","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199942","url":null,"abstract":"Future large scale analog computational systems will have to cope with manufacturing defects and mismatch in individual components. The author argues that current-mode design techniques, and in particular minimal designs at the transistor level are consistent with future manufacturing requirements for wafer scale analog systems.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114292088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199957
Yung-Yuan Chen, S. Upadhyaya
The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. The authors present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Their model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate their model are discussed.<>
{"title":"A new approach to modeling the performance of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy","authors":"Yung-Yuan Chen, S. Upadhyaya","doi":"10.1109/DFTVS.1991.199957","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199957","url":null,"abstract":"The on-chip redundancy left unused in a fault tolerant system after successfully reconfiguring and eliminating the manufacturing defects is called residual redundancy. This redundancy can be used to improve the operational reliability of the system. The authors present a new hierarchical model to analyze the effect of residual redundancy on performance improvement of a class of fault tolerant VLSI/WSI systems based on multiple-level redundancy. Their model emphasizes the effect of support circuit (interconnection) failures on system reliability, a practical issue of great concern in WSI technology. Results of a simulation conducted to validate their model are discussed.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133768038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199951
W. Siu
MCMs are touted as the emerging challenge to monolithic VLSIs. The purported driving forces are performance and economics. While the potentials are attractive, many practical problems remain before MCMs become viable. Furthermore, it is not at clear that MCMs will replace monolithic VLSIs as suggested. The author contrasts these technologies. Using the implementation of a CPU function as an example, he examines the evolution of performance, yields, economics, of both the VLSI implementation and the MCM alternative. It is evident that, at the present time, the lack of a well-developed MCM technical and manufacturing infrastructure limits its penetration. An agenda to address these concerns will be presented. He concludes that MCM is an emerging technology that builds on the continued success of monolithic VLSIs and will augment rather than replace VLSIs.<>
{"title":"Monolithic VLSI vs. MCM a perspective on performance, yield, and manufacturing","authors":"W. Siu","doi":"10.1109/DFTVS.1991.199951","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199951","url":null,"abstract":"MCMs are touted as the emerging challenge to monolithic VLSIs. The purported driving forces are performance and economics. While the potentials are attractive, many practical problems remain before MCMs become viable. Furthermore, it is not at clear that MCMs will replace monolithic VLSIs as suggested. The author contrasts these technologies. Using the implementation of a CPU function as an example, he examines the evolution of performance, yields, economics, of both the VLSI implementation and the MCM alternative. It is evident that, at the present time, the lack of a well-developed MCM technical and manufacturing infrastructure limits its penetration. An agenda to address these concerns will be presented. He concludes that MCM is an emerging technology that builds on the continued success of monolithic VLSIs and will augment rather than replace VLSIs.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132803394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199944
C. Stapper
Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of translating defect-monitor data to memory-chip faults eliminates the need for yield-model formulas, making possible accurate modeling of the faults that can be fixed with redundant circuits or other fault-tolerance techniques. This results in loosely coupled distributions instead of the multivariate distributions used until now for such modeling. Furthermore, the yields of array islands with their own redundant word and bit lines are combined using a new yield formula. Examples of the use of this technique for dynamic random-access memory (DRAM) chips are given. Finally, a simplified pragmatic approximation technique is discussed.<>
{"title":"Improved yield models for fault-tolerant random-access memory chips","authors":"C. Stapper","doi":"10.1109/DFTVS.1991.199944","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199944","url":null,"abstract":"Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of translating defect-monitor data to memory-chip faults eliminates the need for yield-model formulas, making possible accurate modeling of the faults that can be fixed with redundant circuits or other fault-tolerance techniques. This results in loosely coupled distributions instead of the multivariate distributions used until now for such modeling. Furthermore, the yields of array islands with their own redundant word and bit lines are combined using a new yield formula. Examples of the use of this technique for dynamic random-access memory (DRAM) chips are given. Finally, a simplified pragmatic approximation technique is discussed.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126753486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199948
Z. Koren, I. Koren
Many factors contribute the the cost of manufacturing integrated circuits. These include the yield of the design IC, the complexity of its testing, the packaging cost, etc. and they all must be taken into account when designing a defect tolerant integrated circuit. The authors present a mathematical model which includes all major factors contributing to the cost of manufacturing ICs. This model allows the determination of the design which maximizes the expected profit rather than maximizing the yield. Numerical examples illustrating the proposed model are also presented.<>
{"title":"A model for enhanced manufacturability of defect tolerant integrated circuits","authors":"Z. Koren, I. Koren","doi":"10.1109/DFTVS.1991.199948","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199948","url":null,"abstract":"Many factors contribute the the cost of manufacturing integrated circuits. These include the yield of the design IC, the complexity of its testing, the packaging cost, etc. and they all must be taken into account when designing a defect tolerant integrated circuit. The authors present a mathematical model which includes all major factors contributing to the cost of manufacturing ICs. This model allows the determination of the design which maximizes the expected profit rather than maximizing the yield. Numerical examples illustrating the proposed model are also presented.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121725425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199961
J. Zubairi, G.L. Craig
Inductive Fault Analysis is extended to consider localized spot defects in CMOS VLSI circuits which impact circuit timing performance. A scheme of deterministic introduction of spot defects into layouts of combinational logic circuits is described. A methodology and tool is developed to characterize delay defects resulting from missing and extra spot defects and to generate realistic delay defect distribution.<>
{"title":"A bottom-up methodology to characterize delay faults","authors":"J. Zubairi, G.L. Craig","doi":"10.1109/DFTVS.1991.199961","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199961","url":null,"abstract":"Inductive Fault Analysis is extended to consider localized spot defects in CMOS VLSI circuits which impact circuit timing performance. A scheme of deterministic introduction of spot defects into layouts of combinational logic circuits is described. A methodology and tool is developed to characterize delay defects resulting from missing and extra spot defects and to generate realistic delay defect distribution.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116234833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-11-18DOI: 10.1109/DFTVS.1991.199960
R. Velazco, B. Martinet
The last generation of 32-bit microprocessors seems 'to ring the knell' of functional test methods. Indeed, those based on fault hypothesis cannot cope with the technological reality; the other ones (ad hoc tests, systematic test, . . .) are overwhelmed by the very large number of cases (instructions) to be analyzed. The authors present a pragmatic approach that attempts to resolve this critical problem: physical faults are injected by means of a microcutting laser equipment on a set of good circuits in order to evaluate the efficiency of different test sequences. This approach is illustrated by an actual experiment performed on more than an hundred of 68000 microprocessors.<>
{"title":"Physical fault injection: a suitable method for the evaluation of functional test efficiency","authors":"R. Velazco, B. Martinet","doi":"10.1109/DFTVS.1991.199960","DOIUrl":"https://doi.org/10.1109/DFTVS.1991.199960","url":null,"abstract":"The last generation of 32-bit microprocessors seems 'to ring the knell' of functional test methods. Indeed, those based on fault hypothesis cannot cope with the technological reality; the other ones (ad hoc tests, systematic test, . . .) are overwhelmed by the very large number of cases (instructions) to be analyzed. The authors present a pragmatic approach that attempts to resolve this critical problem: physical faults are injected by means of a microcutting laser equipment on a set of good circuits in order to evaluate the efficiency of different test sequences. This approach is illustrated by an actual experiment performed on more than an hundred of 68000 microprocessors.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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