A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406902

Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh

引用次数: 3

Abstract

A power-efficiency and speed-enhancing technique for binary-search ADCs is presented. Asynchronous timing and reduced-count binary-search architecture is implemented to achieve a high-speed operation. The distributed track-and-hold circuit is applied to relax the ENOB degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was simulated in a 90nm CMOS technology. It consumes 2.7 mW from a 1.2 V supply. The ADC core occupies an active area of 0.012 mm2. With the post-layout simulation results, the SNDR and SFDR are 30 dB and 40 dB respectively. The equivalent ENOB is 4.55 b at the Nyquist-rate input. Its FoM is 115 fJ/conversion-step.

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基于90nm数字CMOS的5-b 1-GS/s 2.7 mw二值搜索ADC

提出了一种提高二进制搜索adc功率效率和速度的技术。实现了异步计时和减少计数的二进制搜索架构，以实现高速操作。分布式跟踪保持电路用于缓解由比较器反扰噪声和动态偏移引起的ENOB退化。采用90nm CMOS技术对5-b 1-GS/s ADC原型进行了仿真。它从1.2 V电源消耗2.7兆瓦。ADC核心的有效面积为0.012 mm2。布局后仿真结果显示，SNDR和SFDR分别为30 dB和40 dB。在奈奎斯特速率输入下，等效ENOB为4.55 b。其FoM为115 fJ/转换步长。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 28th IEEE International System-on-Chip Conference (SOCC)

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