Pub Date : 2015-09-08DOI: 10.1109/SOCC.2015.7406911
Xin Yang, S. Sezer
Flow processing is a fundamental element of stateful traffic classification and it has been recognized as an essential factor for delivering today's application-aware network operations and security services. The basic function within a flow processing engine is to search and maintain a flow table, create new flow entries if no entry matches and associate each entry with flow states and actions for future queries. Network state information on a per-flow basis must be managed in an efficient way to enable Ethernet frame transmissions at 40 Gbit/s (Gbps) and 100 Gbps in the near future. This paper presents a hardware solution of flow state management for implementing large-scale flow tables on popular computer memories using DDR3 SDRAMs. Working with a dedicated flow lookup table at over 90 million lookups per second, the proposed system is able to manage 512-bit state information at run time.
{"title":"Per-flow state management technique for high-speed networks","authors":"Xin Yang, S. Sezer","doi":"10.1109/SOCC.2015.7406911","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406911","url":null,"abstract":"Flow processing is a fundamental element of stateful traffic classification and it has been recognized as an essential factor for delivering today's application-aware network operations and security services. The basic function within a flow processing engine is to search and maintain a flow table, create new flow entries if no entry matches and associate each entry with flow states and actions for future queries. Network state information on a per-flow basis must be managed in an efficient way to enable Ethernet frame transmissions at 40 Gbit/s (Gbps) and 100 Gbps in the near future. This paper presents a hardware solution of flow state management for implementing large-scale flow tables on popular computer memories using DDR3 SDRAMs. Working with a dedicated flow lookup table at over 90 million lookups per second, the proposed system is able to manage 512-bit state information at run time.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116043769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406924
Shufan Yang, Renfa Li, Qiang Wu
Visual attention is a voluntary mechanism allows human to allocate our sensory and computational resources to the most valuable information embedded in the vast amount of incoming visual data. Neuromorphic prosthetics with high-level cognitive function can be used to complete increasingly sophisticated tasks. Inspired by recent developments in the field of attention modulation, we propose a biological neural attention model for online visual attention and implement this model on Xilinx ZYNQ 7000 System-on-chip system.
{"title":"Modelling visual attention towards embodiment cognition on a reconfigurable and programmable system","authors":"Shufan Yang, Renfa Li, Qiang Wu","doi":"10.1109/SOCC.2015.7406924","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406924","url":null,"abstract":"Visual attention is a voluntary mechanism allows human to allocate our sensory and computational resources to the most valuable information embedded in the vast amount of incoming visual data. Neuromorphic prosthetics with high-level cognitive function can be used to complete increasingly sophisticated tasks. Inspired by recent developments in the field of attention modulation, we propose a biological neural attention model for online visual attention and implement this model on Xilinx ZYNQ 7000 System-on-chip system.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123258662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406955
Zhijian Lu, Hongyi Wang, S. R. Naqvi, H. Fu, Yuji Zhao, Hongjiang Song, J. Christen
Electrochemical Impedance Spectroscopy (EIS) is a label-free method of molecular detection of particular interest for biomedical applications. We aim to create a hand-held, easy to use EIS measurement device, for biomolecular detection. Electrochemical cyclic voltammetry systems help millions of diabetics monitor their blood glucose levels 2-8 times per day, but their use is very limited due to the poor lower limit of detection. The EIS technique can be used to detect a much larger array of biomolecules at very low concentration. Our EIS system generates the magnitude and phase of the impedance from test samples via MATLAB, which provides the real and imaginary components of the impedance. The circuit was integrated on a single chip and fabricated in a standard 0.5 μm CMOS technology. A hand-held EIS measurement system was built using the chip and an Arduino Uno to measure a Randles circuit equivalent over the frequency range from 1 Hz to 2 kHz, the measurement and simulation results show excellent agreement.
{"title":"A point of care electrochemical impedance spectroscopy device","authors":"Zhijian Lu, Hongyi Wang, S. R. Naqvi, H. Fu, Yuji Zhao, Hongjiang Song, J. Christen","doi":"10.1109/SOCC.2015.7406955","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406955","url":null,"abstract":"Electrochemical Impedance Spectroscopy (EIS) is a label-free method of molecular detection of particular interest for biomedical applications. We aim to create a hand-held, easy to use EIS measurement device, for biomolecular detection. Electrochemical cyclic voltammetry systems help millions of diabetics monitor their blood glucose levels 2-8 times per day, but their use is very limited due to the poor lower limit of detection. The EIS technique can be used to detect a much larger array of biomolecules at very low concentration. Our EIS system generates the magnitude and phase of the impedance from test samples via MATLAB, which provides the real and imaginary components of the impedance. The circuit was integrated on a single chip and fabricated in a standard 0.5 μm CMOS technology. A hand-held EIS measurement system was built using the chip and an Arduino Uno to measure a Randles circuit equivalent over the frequency range from 1 Hz to 2 kHz, the measurement and simulation results show excellent agreement.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"485 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116029172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406916
I. Mostafa, A. Ismail
Inverter-based implementation of operational-transconductance amplifiers (OTAs) is an attractive approach for low-voltage realization of analog sub-systems. However, the high sensitivity of inverter-like amplifiers performance to process and temperature variations limits the achievable performance of the whole system, across process and temperature corners. In this paper, a tuning technique is proposed to maintain inverter-based amplifier performance across process and temperature corners without requiring additional voltage headroom than that required by the inverter circuit. The introduced technique is used to implement a third order continuous-time (CT) ΣΔ analog-to-digital converter (ADC). A 74 dB signal-to-noise and distortion ratio (SNDR) is achieved, for a signal bandwidth of 64 kHz at a sampling frequency of 6.4 MHz, while consuming 400 μA from 0.8 V, supply, in 65 nm CMOS technology.
{"title":"A Tunable Inverter-Based, Low-Voltage OTA for Continuous-Time ΣΔ ADC","authors":"I. Mostafa, A. Ismail","doi":"10.1109/SOCC.2015.7406916","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406916","url":null,"abstract":"Inverter-based implementation of operational-transconductance amplifiers (OTAs) is an attractive approach for low-voltage realization of analog sub-systems. However, the high sensitivity of inverter-like amplifiers performance to process and temperature variations limits the achievable performance of the whole system, across process and temperature corners. In this paper, a tuning technique is proposed to maintain inverter-based amplifier performance across process and temperature corners without requiring additional voltage headroom than that required by the inverter circuit. The introduced technique is used to implement a third order continuous-time (CT) ΣΔ analog-to-digital converter (ADC). A 74 dB signal-to-noise and distortion ratio (SNDR) is achieved, for a signal bandwidth of 64 kHz at a sampling frequency of 6.4 MHz, while consuming 400 μA from 0.8 V, supply, in 65 nm CMOS technology.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116532769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406954
Y. Huan, Ning Ma, S. Blixt, Z. Zou, Lirong Zheng
This paper presents a SoC design that combines general purpose control and application-specific acceleration within a reconfigurable ASIP core for Internet-of-Things applications. Sufficient processing capability and re-configurability are provided by highly customizable data path and efficient sequence control loop. By fully utilizing the data path of proposed architecture, the processor significantly reduces >4X code size and offers superior performance compared with MSP430 and Atmega128 in FIR and Whetstone benchmarks. More than 10X speedup can be obtained in executing encryption algorithms by optimized micro-instructions without extra hardware accelerators. Fabricated in 0.18 μm CMOS, our SoC's energy efficiency beats most of the microcontrollers with a value as low as 61 μA/MHz.
{"title":"A 61 μA/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things","authors":"Y. Huan, Ning Ma, S. Blixt, Z. Zou, Lirong Zheng","doi":"10.1109/SOCC.2015.7406954","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406954","url":null,"abstract":"This paper presents a SoC design that combines general purpose control and application-specific acceleration within a reconfigurable ASIP core for Internet-of-Things applications. Sufficient processing capability and re-configurability are provided by highly customizable data path and efficient sequence control loop. By fully utilizing the data path of proposed architecture, the processor significantly reduces >4X code size and offers superior performance compared with MSP430 and Atmega128 in FIR and Whetstone benchmarks. More than 10X speedup can be obtained in executing encryption algorithms by optimized micro-instructions without extra hardware accelerators. Fabricated in 0.18 μm CMOS, our SoC's energy efficiency beats most of the microcontrollers with a value as low as 61 μA/MHz.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122520138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406990
Qi Hu, Kejun Wu, Peng Liu
Main-stream general-purpose microprocessors integrate a growing number of cores on-chip, requiring high-performance interconnects and efficient cache coherence for data transmission and sharing. Conventional directory-based cache coherence has high indirection overhead, which adds to the critical path of data requests and lowers overall system performance. In fact, with globally shared high-performance interconnects, cache coherence could be optimized and the indirection overhead could be relieved. This paper explores the use of multi-band transmission lines to implement globally shared interconnects. Taking advantage of the aggregate frequency band resources, the proposed interconnect supports efficient multi-cast, and helps improve the efficiency of cache coherence with augmented parallelism. Coherence indirections are avoided, and we have seen an average of 17% boost in application performance, as well as an average of 18% throughput improvement compared to an implementation of conventional cache coherence on single-band transmission line based interconnects.
{"title":"Exploiting multi-band transmission line interconnects to improve the efficiency of cache coherence in multiprocessor system-on-chip","authors":"Qi Hu, Kejun Wu, Peng Liu","doi":"10.1109/SOCC.2015.7406990","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406990","url":null,"abstract":"Main-stream general-purpose microprocessors integrate a growing number of cores on-chip, requiring high-performance interconnects and efficient cache coherence for data transmission and sharing. Conventional directory-based cache coherence has high indirection overhead, which adds to the critical path of data requests and lowers overall system performance. In fact, with globally shared high-performance interconnects, cache coherence could be optimized and the indirection overhead could be relieved. This paper explores the use of multi-band transmission lines to implement globally shared interconnects. Taking advantage of the aggregate frequency band resources, the proposed interconnect supports efficient multi-cast, and helps improve the efficiency of cache coherence with augmented parallelism. Coherence indirections are avoided, and we have seen an average of 17% boost in application performance, as well as an average of 18% throughput improvement compared to an implementation of conventional cache coherence on single-band transmission line based interconnects.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126505717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406887
M. Ismail
This talk will focus on Systems-on-Chip (SoCs) presented as part of the UAE SRC (Semiconductor Research Corp) Center of Excellence on Energy Efficient Electronic Systems (aka ACE4S http://www.src.org/program/grc/ace4s/) involving researchers from 5 UAE Universities looking at developing new technologies aiming at innovative self-powered wireless sensing and monitoring SoC platforms. The research targets applications in self-powered chip sets for use in public health, ambient intelligence, safety and security and water quality. ACE4S is the first SRC center of excellence outside the US. One such application, which we will discuss in details, is a novel SoC platform for wearable health care. More specifically we will present a novel fully integrated ECG signal processing system for the prediction of ventricular arrhythmia using a unique set of ECG features extracted from two consecutive cardiac cycles. Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training, test and validation sets to evaluate the performance of the proposed system. The system achieved an accuracy of 99%. The ECG signal is sensed using a flexible, dry, MEMS-based technology and the system is powered up by harvesting human thermal energy. The system architecture is implemented in Global foundries' 65 nm CMOS process, occupies 0.112 mm2 and consumes 2.78 micro Watt at an operating frequency of 10 KHz and from a supply voltage of 1.2V. To our knowledge, this is the first SoC implementation of an ECGbased processor that is capable of predicting ventricular arrhythmia hours before the onset and with an accuracy of 99%.
{"title":"Session T3B: Tutorial: A self-powered biomedical SoC for wearable health care","authors":"M. Ismail","doi":"10.1109/SOCC.2015.7406887","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406887","url":null,"abstract":"This talk will focus on Systems-on-Chip (SoCs) presented as part of the UAE SRC (Semiconductor Research Corp) Center of Excellence on Energy Efficient Electronic Systems (aka ACE4S http://www.src.org/program/grc/ace4s/) involving researchers from 5 UAE Universities looking at developing new technologies aiming at innovative self-powered wireless sensing and monitoring SoC platforms. The research targets applications in self-powered chip sets for use in public health, ambient intelligence, safety and security and water quality. ACE4S is the first SRC center of excellence outside the US. One such application, which we will discuss in details, is a novel SoC platform for wearable health care. More specifically we will present a novel fully integrated ECG signal processing system for the prediction of ventricular arrhythmia using a unique set of ECG features extracted from two consecutive cardiac cycles. Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training, test and validation sets to evaluate the performance of the proposed system. The system achieved an accuracy of 99%. The ECG signal is sensed using a flexible, dry, MEMS-based technology and the system is powered up by harvesting human thermal energy. The system architecture is implemented in Global foundries' 65 nm CMOS process, occupies 0.112 mm2 and consumes 2.78 micro Watt at an operating frequency of 10 KHz and from a supply voltage of 1.2V. To our knowledge, this is the first SoC implementation of an ECGbased processor that is capable of predicting ventricular arrhythmia hours before the onset and with an accuracy of 99%.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132515608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406944
G. Stark
Software Defined Networks (SDN) are a major development in communications, providing a means for controlling and reducing the complexity of managing the many protocols and layers that are in modern networks, and aiding virtualization of networks using a myriad of tunneling techniques. As with most complex systems there are (at least) two perspectives on SDN: a view from the hardware, where SDN is about feeding the silicon systems that are driven by the slow evolution of network silicon progress; and a view from above, a software perspective, where the requirements come from replicating and enhancing the features used in legacy equipment. The reconciliation of these two viewpoints is difficult at a network appliance level, and even harder at an SOC level. We will explore these two perspectives and this reconciliation in various SOC architectures, and investigate how these various architectures satisfy the needs of the networks.
{"title":"Unicorns and centaurs: Architecting SOCs for software defined networking","authors":"G. Stark","doi":"10.1109/SOCC.2015.7406944","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406944","url":null,"abstract":"Software Defined Networks (SDN) are a major development in communications, providing a means for controlling and reducing the complexity of managing the many protocols and layers that are in modern networks, and aiding virtualization of networks using a myriad of tunneling techniques. As with most complex systems there are (at least) two perspectives on SDN: a view from the hardware, where SDN is about feeding the silicon systems that are driven by the slow evolution of network silicon progress; and a view from above, a software perspective, where the requirements come from replicating and enhancing the features used in legacy equipment. The reconciliation of these two viewpoints is difficult at a network appliance level, and even harder at an SOC level. We will explore these two perspectives and this reconciliation in various SOC architectures, and investigate how these various architectures satisfy the needs of the networks.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133313256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/SOCC.2015.7406961
Z. Jiang, D. Xiang, Kele Shen
With the chip size entering the micro-nano level, the increasing power consumption during the chip testing process becomes the bottleneck of chip production and testing. Prior work has been mainly focused on reducing power dissipation in either shift cycle or capture cycle, however, there has been limited work on reducing the peak power in both shift and capture cycles at the same time. Moreover, there has been no work on the problem of capture power controllability. This paper proposes a new power-aware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time with small area overhead. Meanwhile, we devise sophisticated algorithms of dependency checking and scan segments partitioning, which can directly reduce simultaneously switching activity of flip-flops by iterative optimizing scan segments grouping. To the best of our knowledge, this paper is the first of its kind to study the problem of power controllability considering both structure dependency and clock trees' impact. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed architecture.
{"title":"A scan segmentation architecture for power controllability and reduction","authors":"Z. Jiang, D. Xiang, Kele Shen","doi":"10.1109/SOCC.2015.7406961","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406961","url":null,"abstract":"With the chip size entering the micro-nano level, the increasing power consumption during the chip testing process becomes the bottleneck of chip production and testing. Prior work has been mainly focused on reducing power dissipation in either shift cycle or capture cycle, however, there has been limited work on reducing the peak power in both shift and capture cycles at the same time. Moreover, there has been no work on the problem of capture power controllability. This paper proposes a new power-aware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time with small area overhead. Meanwhile, we devise sophisticated algorithms of dependency checking and scan segments partitioning, which can directly reduce simultaneously switching activity of flip-flops by iterative optimizing scan segments grouping. To the best of our knowledge, this paper is the first of its kind to study the problem of power controllability considering both structure dependency and clock trees' impact. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed architecture.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124221157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper analyzes and designs inductive coupling power delivery (ICPD) system for 3-D stacked chips in SMIC 65-nm CMOS process. Two shapes of inductors, the rectangular and the octagonal inductor, are compared. Fully customized octagonal inductors with 500 μm diameter are optimized to improve power delivery efficiency. An octagonal inductor based ICPD consisting transmitter and receiver circuit is proposed by using H-bridge architecture and NMOS cross-gate rectifier. Simulation results show that the received power is 12 mW with a delivery efficiency of 12% and a power density of 59.5 mW/mm2. In order to achieve the higher power at the receiver side in some special applications, a four parallel connected inductors based wireless power link is designed, which reaches 34.2 mW.
{"title":"Analysis and design of high performance wireless power delivery using on-chip octagonal inductor in 65-nm CMOS","authors":"Weijun Mao, Liusheng Sun, Junwei Xu, Jiajia Wu, Xiaolei Zhu","doi":"10.1109/SOCC.2015.7406992","DOIUrl":"https://doi.org/10.1109/SOCC.2015.7406992","url":null,"abstract":"This paper analyzes and designs inductive coupling power delivery (ICPD) system for 3-D stacked chips in SMIC 65-nm CMOS process. Two shapes of inductors, the rectangular and the octagonal inductor, are compared. Fully customized octagonal inductors with 500 μm diameter are optimized to improve power delivery efficiency. An octagonal inductor based ICPD consisting transmitter and receiver circuit is proposed by using H-bridge architecture and NMOS cross-gate rectifier. Simulation results show that the received power is 12 mW with a delivery efficiency of 12% and a power density of 59.5 mW/mm2. In order to achieve the higher power at the receiver side in some special applications, a four parallel connected inductors based wireless power link is designed, which reaches 34.2 mW.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116275847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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