A high speed and low power content-addressable memory(CAM) using pipelined scheme

Abstract

This paper presents a novel technique to design high performance Content-addressable memories(CAMs), with lower power and latency as compared to other similar structures. The first technique is to pipeline the search operation by distributing single matching operation into several segments for different search-line registers. Speed is improved significantly since four search-line registers are comparing in parallel. Meanwhile, by disabling the subsequent segments, the power consumption is also reduced. The second technique is to improve the speed further by using multi-bank search data registers structure. The experimental results show that up to 37.32% power savings can be obtained and 90.79% time can be shrieked as compared to conventional NOR-type CAM design.