CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS

Abstract

Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.