An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applications

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI:10.1109/SOCC.2004.1362387

Y. Gang, T. Arslan, A. Erdogan

引用次数: 0

Abstract

The authors present a reformulation based architecture for threshold selection in adaptive foward error correction (FEC) decoding in wireless applications. The reformulation technique results in an efficient VLSI architecture with a significant reduction in hardware complexity. The paper describes the reformulation technique, its applications on the architecture for adaptive forward error correction (FEC) decoding algorithm and its implementations. We demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric unit (PMU).

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一种有效的基于重构的自适应前向纠错译码体系结构

提出了一种基于重构的自适应前向纠错(FEC)译码门限选择体系结构。重构技术产生了高效的VLSI架构，并显著降低了硬件复杂性。本文介绍了重构技术及其在自适应前向纠错(FEC)译码算法体系结构中的应用及其实现。我们证明，除了显著降低数据路径复杂性之外，路径度量单位(PMU)的存储也减少了25%到47%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International SOC Conference, 2004. Proceedings.

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