Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362449
S. Bandi, P. R. Mukund
A compensation technique to correct the mismatch in the current mirrors due to transistor process parameter variations is presented. The compensation is achieved by varying the drain voltage of the mirroring transistors. This method is implemented by just adding a single transistor, operating in the linear region at the drain of the mirroring transistor. The circuit is simulated for a threshold voltage mismatch of /spl plusmn/10%. The simulation results show that the percentage error in the mirrored currents reduced from 48% to 3% for a threshold voltage mismatch of +10% and from 70% to 10% for a threshold voltage mismatch of -10%, for a wide range of input current values. The affect of temperature on the performance of the circuit is studied. The power consumption with and without the compensation transistor is compared. The compensation technique is successfully implemented in a CMOS image sensor.
{"title":"A compensation technique for transistor mismatch in current mirrors","authors":"S. Bandi, P. R. Mukund","doi":"10.1109/SOCC.2004.1362449","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362449","url":null,"abstract":"A compensation technique to correct the mismatch in the current mirrors due to transistor process parameter variations is presented. The compensation is achieved by varying the drain voltage of the mirroring transistors. This method is implemented by just adding a single transistor, operating in the linear region at the drain of the mirroring transistor. The circuit is simulated for a threshold voltage mismatch of /spl plusmn/10%. The simulation results show that the percentage error in the mirrored currents reduced from 48% to 3% for a threshold voltage mismatch of +10% and from 70% to 10% for a threshold voltage mismatch of -10%, for a wide range of input current values. The affect of temperature on the performance of the circuit is studied. The power consumption with and without the compensation transistor is compared. The compensation technique is successfully implemented in a CMOS image sensor.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362457
Junmou Zhang, E. Friedman
An effective mutual inductance is proposed in this paper to efficiently describe the inductive interactions among coupled signal lines. An efficient estimate of the crosstalk noise among multiple coupled RLC interconnects is achieved by simplifying the system of coupled lines into only two coupled RLC interconnects. The concept of an effective mutual inductance is further applied to a shielding technique, providing guidelines for inserting shields to reduce crosstalk noise in the presence of both capacitive and inductive coupling.
{"title":"Mutual inductance modeling for multiple RLC interconnects with application to shield insertion","authors":"Junmou Zhang, E. Friedman","doi":"10.1109/SOCC.2004.1362457","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362457","url":null,"abstract":"An effective mutual inductance is proposed in this paper to efficiently describe the inductive interactions among coupled signal lines. An efficient estimate of the crosstalk noise among multiple coupled RLC interconnects is achieved by simplifying the system of coupled lines into only two coupled RLC interconnects. The concept of an effective mutual inductance is further applied to a shielding technique, providing guidelines for inserting shields to reduce crosstalk noise in the presence of both capacitive and inductive coupling.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122386789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362331
Imran Ahmed, T. Arslan, S. Khawam
This paper describes efficient video transmission over Bluetooth using reconfigurable architectures. Currently most of the hardware solutions in research utilize MPEG-4 compression algorithms to compensate for the limited bandwidth available on Bluetooth channel. The reconfigurable MPEG-4 and error correction encoders and decoder blocks presented in this paper not only provide flexibility but also means where dynamic or static mapping of different algorithms can be done to meet various performance constraints vis-a-vis reduced silicon area, reduced power, improved speed and error correction.
{"title":"Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1/spl trade/ standard [architecurtes read architectures]","authors":"Imran Ahmed, T. Arslan, S. Khawam","doi":"10.1109/SOCC.2004.1362331","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362331","url":null,"abstract":"This paper describes efficient video transmission over Bluetooth using reconfigurable architectures. Currently most of the hardware solutions in research utilize MPEG-4 compression algorithms to compensate for the limited bandwidth available on Bluetooth channel. The reconfigurable MPEG-4 and error correction encoders and decoder blocks presented in this paper not only provide flexibility but also means where dynamic or static mapping of different algorithms can be done to meet various performance constraints vis-a-vis reduced silicon area, reduced power, improved speed and error correction.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129530553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362432
Tomaz Feliciian, S. Furber
This paper presents an asynchronous on-chip network router with quality-of-service (QoS) support. The router uses a virtual channel architecture with a priority-based scheduler to differentiate between multiple connections with various QoS requirements sharing the same physical channel. A gate-level prototype of the router has been built and its functionality and performance evaluated. The simulations show that the router is capable of offering a high-level of QoS within the capacity limitations of the network.
{"title":"An asynchronous on-chip network router with quality-of-service (QoS) support","authors":"Tomaz Feliciian, S. Furber","doi":"10.1109/SOCC.2004.1362432","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362432","url":null,"abstract":"This paper presents an asynchronous on-chip network router with quality-of-service (QoS) support. The router uses a virtual channel architecture with a priority-based scheduler to differentiate between multiple connections with various QoS requirements sharing the same physical channel. A gate-level prototype of the router has been built and its functionality and performance evaluated. The simulations show that the router is capable of offering a high-level of QoS within the capacity limitations of the network.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122267073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362461
Qiurong He, M. Feng
A bang-bang half-rate architecture is presented for high-speed random input clock and data recovery. In contrast to the conventional half-rate architectures, which contain two separated full-rate phase detectors and additional complicated logic and clock distribution circuits, the proposed architecture utilizes a genuine half-rate phase detector and eliminates the logic circuits. Therefore, it significantly simplifies the circuit complexity. A SiGe clock and data recovery circuit using this architecture is designed with 40Gb/s input data rate.
{"title":"A novel half-rate architecture for high-speed clock and data recovery","authors":"Qiurong He, M. Feng","doi":"10.1109/SOCC.2004.1362461","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362461","url":null,"abstract":"A bang-bang half-rate architecture is presented for high-speed random input clock and data recovery. In contrast to the conventional half-rate architectures, which contain two separated full-rate phase detectors and additional complicated logic and clock distribution circuits, the proposed architecture utilizes a genuine half-rate phase detector and eliminates the logic circuits. Therefore, it significantly simplifies the circuit complexity. A SiGe clock and data recovery circuit using this architecture is designed with 40Gb/s input data rate.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131933631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362410
M. Konakov, Jae-Wook Lee, Jung-Hyun Lee, Eun-Jin Ryu, Eingseob Cho, Jungeun Lee, Hyunsu Chae, Jeongwon Lee
New mixed analog/digital PRML (partial response maximum likelihood) architecture for the optical drive system is presented. In order to realize high speed, low power and low cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits to provide high speed and low power data detection for optical data storage system. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and area by 42%, therefore it provides high speed, low power and low cost SOC solution for the future optical drive system. A test chip produced is fabricated using 0.18 /spl mu/m CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.
{"title":"High speed mixed analog/digital PRML architecture for optical data storage system","authors":"M. Konakov, Jae-Wook Lee, Jung-Hyun Lee, Eun-Jin Ryu, Eingseob Cho, Jungeun Lee, Hyunsu Chae, Jeongwon Lee","doi":"10.1109/SOCC.2004.1362410","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362410","url":null,"abstract":"New mixed analog/digital PRML (partial response maximum likelihood) architecture for the optical drive system is presented. In order to realize high speed, low power and low cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits to provide high speed and low power data detection for optical data storage system. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and area by 42%, therefore it provides high speed, low power and low cost SOC solution for the future optical drive system. A test chip produced is fabricated using 0.18 /spl mu/m CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130189296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362405
R. Ayoub, Peter Petrov, A. Orailoglu
In this paper we present a coding framework for a low energy instruction bus for embedded processors. The encoder exploits application-specific knowledge regarding program hot-spots to generate codewords that deliver savings in power and to furthermore provide concurrent detection of errors. Power savings can be obtained through the use of codewords that reduce the switching activity on the bus. The analysis shows that generating codewords that prohibit the occurrence of three consecutive transitions in three adjacent lines is fundamental to capturing the worst-case crosstalk faults in the bus lines at run time, thus improving the overall reliability of the bus. The desired codewords can be generated through a set of simple prespecified transformations. The detailed analysis we outline shows that the presented transformations are optimal. The proposed encoding scheme is dynamically reprogrammable, thus targeting code particularities effectively. The restriction to a simple yet efficient set of transformations reduces the required storage capacity and eases reprogrammability while achieving these objectives. Extensive experimental analysis on numerical and DSP codes indicates significant improvements in power savings.
{"title":"Application specific instruction memory transformations for power efficient, fault resilient embedded processors","authors":"R. Ayoub, Peter Petrov, A. Orailoglu","doi":"10.1109/SOCC.2004.1362405","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362405","url":null,"abstract":"In this paper we present a coding framework for a low energy instruction bus for embedded processors. The encoder exploits application-specific knowledge regarding program hot-spots to generate codewords that deliver savings in power and to furthermore provide concurrent detection of errors. Power savings can be obtained through the use of codewords that reduce the switching activity on the bus. The analysis shows that generating codewords that prohibit the occurrence of three consecutive transitions in three adjacent lines is fundamental to capturing the worst-case crosstalk faults in the bus lines at run time, thus improving the overall reliability of the bus. The desired codewords can be generated through a set of simple prespecified transformations. The detailed analysis we outline shows that the presented transformations are optimal. The proposed encoding scheme is dynamically reprogrammable, thus targeting code particularities effectively. The restriction to a simple yet efficient set of transformations reduces the required storage capacity and eases reprogrammability while achieving these objectives. Extensive experimental analysis on numerical and DSP codes indicates significant improvements in power savings.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134322457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362447
V. Gupta, G. Rincón-Mora, P. Raha
Linear regulators are critical analog blocks that shield a system from fluctuations in supply rails and the importance of determining their power supply rejection (PSR) performance is magnified in SoC systems, given their inherently noisy environments. In this work, a simple, intuitive, voltage divider model is introduced to analyze the PSR of linear regulators, from which design guidelines for obtaining high PSR performance are derived. The PSR of regulators that use PMOS output stages for low drop-out (LDO), crucial for modern low-voltage systems, is enhanced by error amplifiers which present a supply-correlated ripple at the gate of the PMOS pass device. On the other hand, amplifiers that suppress the supply ripple at their output are optimal for NMOS output stages since the source is now free from output ripple. A better PSR bandwidth, at the cost of dc PSR, can be obtained by interchanging the amplifiers in the two cases. It has also been proved that the dc PSR, its dominant frequency breakpoint (where performance starts to degrade), and three subsequent breakpoints are determined by the dc open-loop gain, error amplifier bandwidth, unity-gain frequency (UGF) of the system, output pole, and ESR zero, respectively. These results were verified with SPICE simulations using BSIM3 models for the TSMC 0.35 /spl mu/m CMOS process from MOSIS.
{"title":"Analysis and design of monolithic, high PSR, linear regulators for SoC applications","authors":"V. Gupta, G. Rincón-Mora, P. Raha","doi":"10.1109/SOCC.2004.1362447","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362447","url":null,"abstract":"Linear regulators are critical analog blocks that shield a system from fluctuations in supply rails and the importance of determining their power supply rejection (PSR) performance is magnified in SoC systems, given their inherently noisy environments. In this work, a simple, intuitive, voltage divider model is introduced to analyze the PSR of linear regulators, from which design guidelines for obtaining high PSR performance are derived. The PSR of regulators that use PMOS output stages for low drop-out (LDO), crucial for modern low-voltage systems, is enhanced by error amplifiers which present a supply-correlated ripple at the gate of the PMOS pass device. On the other hand, amplifiers that suppress the supply ripple at their output are optimal for NMOS output stages since the source is now free from output ripple. A better PSR bandwidth, at the cost of dc PSR, can be obtained by interchanging the amplifiers in the two cases. It has also been proved that the dc PSR, its dominant frequency breakpoint (where performance starts to degrade), and three subsequent breakpoints are determined by the dc open-loop gain, error amplifier bandwidth, unity-gain frequency (UGF) of the system, output pole, and ESR zero, respectively. These results were verified with SPICE simulations using BSIM3 models for the TSMC 0.35 /spl mu/m CMOS process from MOSIS.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115927356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362342
Sunny Nahata, Kyusun Choi, Jincheol Yoo
A high-speed and small-area power and resolution adaptive flash ADC is presented. The high-speed power and resolution adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 /spl mu/m and 0.07 /spl mu/m CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.
{"title":"A high-speed power and resolution adaptive flash analog-to-digital converter","authors":"Sunny Nahata, Kyusun Choi, Jincheol Yoo","doi":"10.1109/SOCC.2004.1362342","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362342","url":null,"abstract":"A high-speed and small-area power and resolution adaptive flash ADC is presented. The high-speed power and resolution adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 /spl mu/m and 0.07 /spl mu/m CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115124405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-30DOI: 10.1109/SOCC.2004.1362471
Jiandong Ge, A. Dinh
A high gain bandpass filter was designed as a channel-select filter for applications around 3.8GHz. Three stages of 2nd order were cascaded to have a high image rejection filter with an adjustable bandwidth. An experimental filter designed using standard 0.18/spl mu/m CMOS occupies an area of 0.9/spl times/0.9mm/sup 2/. This high performance filter provides a selected center frequency ranging from 3.6GHz to 3.8GHz, an image-rejection of 50dB and a tunable Q from 25 to 50 for bandwidth adjustment. The filter achieves a 15dB gain from a 1.8V supply.
{"title":"A 3.8Ghz channel-select filter using 0.18/spl mu/m CMOS","authors":"Jiandong Ge, A. Dinh","doi":"10.1109/SOCC.2004.1362471","DOIUrl":"https://doi.org/10.1109/SOCC.2004.1362471","url":null,"abstract":"A high gain bandpass filter was designed as a channel-select filter for applications around 3.8GHz. Three stages of 2nd order were cascaded to have a high image rejection filter with an adjustable bandwidth. An experimental filter designed using standard 0.18/spl mu/m CMOS occupies an area of 0.9/spl times/0.9mm/sup 2/. This high performance filter provides a selected center frequency ranging from 3.6GHz to 3.8GHz, an image-rejection of 50dB and a tunable Q from 25 to 50 for bandwidth adjustment. The filter achieves a 15dB gain from a 1.8V supply.","PeriodicalId":184894,"journal":{"name":"IEEE International SOC Conference, 2004. Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117183727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：