Leakage aware SER reduction technique for UDSM logic circuits

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI:10.1109/SOCC.2004.1362357

P. Elakkumanan, Vishwanath Ananthakrishnan, A. Narasimhan, R. Sridhar

引用次数: 0

Abstract

With technology scaling aggressively into the very deep submicron era, leakage power and single event upsets (SEUs) pose serious challenges to circuit designers. Here, we present a technique to reduce the soft error rate (SER) in combinational circuits, with minimal area overhead using minimum leakage input vector (MLIV) leakage reduction technique. Simulation results show significant reduction in area overhead as compared to existing techniques, while reducing the leakage power by nearly 40%.

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UDSM逻辑电路的泄漏感知SER降低技术

随着技术迅速扩展到亚微米时代，泄漏功率和单事件干扰(seu)对电路设计人员提出了严峻的挑战。在这里，我们提出了一种利用最小泄漏输入向量(MLIV)泄漏减少技术，以最小的面积开销来降低组合电路中的软错误率(SER)的技术。仿真结果表明，与现有技术相比，该技术显著降低了面积开销，同时将泄漏功率降低了近40%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International SOC Conference, 2004. Proceedings.

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