3D wafer stack neurocomputing

M. Campbell, S. T. Toborg, S.L. Taylor
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引用次数: 15

Abstract

A family of massively parallel multiple-single-instruction multiple-data (MSIMD) architectures which can be configured to efficiently handle a variety of different neural network models is introduced. The underlying technology is three dimensional wafer scale integration (3D WSI), which provides an ideal medium for constructing low-power hardware tailored for neural network processing. The performance of this prototype is compared with that of enhanced architectures configured with special wafer types to accelerate neural network operations. The design emphasizes the synergy between neural processing functions and the 3D WSI architecture and packaging. Detailed microcode emulations are used to access the impact of different algorithms and architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks.<>
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3D晶圆堆叠神经计算
介绍了一种大规模并行多单指令多数据(MSIMD)体系结构,该体系结构可以有效地处理各种不同的神经网络模型。其基础技术是三维晶圆级集成(3D WSI),为构建适合神经网络处理的低功耗硬件提供了理想的介质。将该原型的性能与配置特殊晶圆类型以加速神经网络运算的增强架构进行了比较。该设计强调神经处理功能与3D WSI架构和封装之间的协同作用。详细的微码仿真用于访问不同算法和架构修改的影响。用于协同视觉集成和多层反向传播的神经网络被映射到各种三维晶圆堆栈上
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Testing constant-geometry FFT arrays for wafer scale integration Use of high dielectric constant insulators for bypass capacitance in WSI and wafer scale hybrid multichip modules 3D wafer stack neurocomputing Algorithmic bus and circuit layout for wafer-scale integration and multichip modules Effect of communication delay on gracefully degradable WSI processor array performance
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