{"title":"3D wafer stack neurocomputing","authors":"M. Campbell, S. T. Toborg, S.L. Taylor","doi":"10.1109/ICWSI.1993.255272","DOIUrl":null,"url":null,"abstract":"A family of massively parallel multiple-single-instruction multiple-data (MSIMD) architectures which can be configured to efficiently handle a variety of different neural network models is introduced. The underlying technology is three dimensional wafer scale integration (3D WSI), which provides an ideal medium for constructing low-power hardware tailored for neural network processing. The performance of this prototype is compared with that of enhanced architectures configured with special wafer types to accelerate neural network operations. The design emphasizes the synergy between neural processing functions and the 3D WSI architecture and packaging. Detailed microcode emulations are used to access the impact of different algorithms and architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1993.255272","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
A family of massively parallel multiple-single-instruction multiple-data (MSIMD) architectures which can be configured to efficiently handle a variety of different neural network models is introduced. The underlying technology is three dimensional wafer scale integration (3D WSI), which provides an ideal medium for constructing low-power hardware tailored for neural network processing. The performance of this prototype is compared with that of enhanced architectures configured with special wafer types to accelerate neural network operations. The design emphasizes the synergy between neural processing functions and the 3D WSI architecture and packaging. Detailed microcode emulations are used to access the impact of different algorithms and architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks.<>