Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255279
M. Syrzycki, L. Carr, G. Chapman, M. Parameswaran
Wafer scale transducer arrays (WSTAs) containing multi-transducer arrays combined with processing circuits are produced using a combination of CMOS technology, silicon micromachining and laser interconnection techniques. A prototype wafer scale visual-to-thermal converter is being developed to convert a visual scene to thermal scene with the same resolution. The basic array is composed of transducer pixels, which combine photodetectors and thermal emitters as transducers, together with signal conditioning and control circuitry. The WSTA redundancy approach is driven by regularity in transducer location and emphasizes local over global transducer sparing.<>
{"title":"A wafer scale visual-to-thermal converter","authors":"M. Syrzycki, L. Carr, G. Chapman, M. Parameswaran","doi":"10.1109/ICWSI.1993.255279","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255279","url":null,"abstract":"Wafer scale transducer arrays (WSTAs) containing multi-transducer arrays combined with processing circuits are produced using a combination of CMOS technology, silicon micromachining and laser interconnection techniques. A prototype wafer scale visual-to-thermal converter is being developed to convert a visual scene to thermal scene with the same resolution. The basic array is composed of transducer pixels, which combine photodetectors and thermal emitters as transducers, together with signal conditioning and control circuitry. The WSTA redundancy approach is driven by regularity in transducer location and emphasizes local over global transducer sparing.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127124956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255245
M. Burnus, H. Taddiken, H.-D. Hartmann, T. Hillmann-Ruge
Configurable interconnection arrays for wafer scale integration (WSI) constitute an application for thin-film multichip modules (MCMs) based on silicon. Laser-formed vertical links allow short cycle times and introduce redundancy into the MCSi (multichip on silicon) technique. As personalization is performed after complete wafer processing, large-volume manufacturing without individual process steps is possible. Laser process parameters developed for a standard CMOS double-level metallization are adapted to a double-level sandwich metallization. Burn-in measurements are carried out with currents up to 150 mA. Laser contacts are found to be suitable for different standard double-level metallizations and for configuration of interconnection arrays.<>
{"title":"Laser personalization of interconnection arrays for hybrid ASICs","authors":"M. Burnus, H. Taddiken, H.-D. Hartmann, T. Hillmann-Ruge","doi":"10.1109/ICWSI.1993.255245","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255245","url":null,"abstract":"Configurable interconnection arrays for wafer scale integration (WSI) constitute an application for thin-film multichip modules (MCMs) based on silicon. Laser-formed vertical links allow short cycle times and introduce redundancy into the MCSi (multichip on silicon) technique. As personalization is performed after complete wafer processing, large-volume manufacturing without individual process steps is possible. Laser process parameters developed for a standard CMOS double-level metallization are adapted to a double-level sandwich metallization. Burn-in measurements are carried out with currents up to 150 mA. Laser contacts are found to be suitable for different standard double-level metallizations and for configuration of interconnection arrays.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125935992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255242
S. Tewksbury, L. Hornak, H. Nariman, S. M. Langsjoen, S. Mcginnis
Two specific issues impacting the eventual application of optical interconnection in full-wafer systems are addressed. The first issue is growth of GaAs semiconductor regions within a silicon wafer scale integration (WSI) or multichip module (MCM) substrate containing high performance silicon CMOS circuitry, in order to cointegrate optical and silicon VLSI devices. The second concerns the addition of VLSI electronics to obtain a detector array which can electronically establish alignment with an incident bundle of optical beams. These issues are considered from the perspective of massively parallel optical interconnections between packaged wafer-level components.<>
{"title":"Cointegration of optoelectronics and submicron CMOS","authors":"S. Tewksbury, L. Hornak, H. Nariman, S. M. Langsjoen, S. Mcginnis","doi":"10.1109/ICWSI.1993.255242","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255242","url":null,"abstract":"Two specific issues impacting the eventual application of optical interconnection in full-wafer systems are addressed. The first issue is growth of GaAs semiconductor regions within a silicon wafer scale integration (WSI) or multichip module (MCM) substrate containing high performance silicon CMOS circuitry, in order to cointegrate optical and silicon VLSI devices. The second concerns the addition of VLSI electronics to obtain a detector array which can electronically establish alignment with an incident bundle of optical beams. These issues are considered from the perspective of massively parallel optical interconnections between packaged wafer-level components.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122427340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255250
Steven D. Millman
It is shown that for typical values of test coverage and yield, increasing the test coverage will have a greater impact on quality for a lower cost than similar increases in yield. This relationship often holds even when the increase in yield is much larger than the increase in test coverage. It must be ensured that the test coverage is based on fault models that accurately describe the behavior of fault chips, and that the simulated faults accurately represent the failures that actually occur.<>
{"title":"Improving quality: yield vs. test coverage (WSI)","authors":"Steven D. Millman","doi":"10.1109/ICWSI.1993.255250","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255250","url":null,"abstract":"It is shown that for typical values of test coverage and yield, increasing the test coverage will have a greater impact on quality for a lower cost than similar increases in yield. This relationship often holds even when the increase in yield is much larger than the increase in test coverage. It must be ensured that the test coverage is based on fault models that accurately describe the behavior of fault chips, and that the simulated faults accurately represent the failures that actually occur.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122791086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255261
R. V. Pelletier, D. Blight, R. McLeod
Methods of improving the probability that a message can be passed from one side of a wafer to another are presented. This is achieved by increasing the number of usable processors in the system or, in other words, lowering the percolation threshold. The impact of several underlying topologies is discussed in terms of a percolation theory framework. Also presented are new routing techniques for message passing in wafer scale integration (WSI) processor arrays. The algorithms forego the shortest path route so as to avoid faulty and congested areas of the network. They are based on a biased random walker approach where the direction each packet travels is determined locally at each processor by a nondeterministic algorithm and a set of bias values. A practical application motivated by improved connectivity in multichip modules is introduced. This method allows for a reconfigurable wafer backplane that provides advantages in bypassing faulty lines in the wafer.<>
{"title":"Fault tolerance in a wafer scale environment","authors":"R. V. Pelletier, D. Blight, R. McLeod","doi":"10.1109/ICWSI.1993.255261","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255261","url":null,"abstract":"Methods of improving the probability that a message can be passed from one side of a wafer to another are presented. This is achieved by increasing the number of usable processors in the system or, in other words, lowering the percolation threshold. The impact of several underlying topologies is discussed in terms of a percolation theory framework. Also presented are new routing techniques for message passing in wafer scale integration (WSI) processor arrays. The algorithms forego the shortest path route so as to avoid faulty and congested areas of the network. They are based on a biased random walker approach where the direction each packet travels is determined locally at each processor by a nondeterministic algorithm and a set of bias values. A practical application motivated by improved connectivity in multichip modules is introduced. This method allows for a reconfigurable wafer backplane that provides advantages in bypassing faulty lines in the wafer.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129823330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255258
J. Salinas, C. Feng, F. Lombardi
Two approaches for testing constant-geometry wafer scale integration (WSI) array architectures used in the computation of the complex N-point fast Fourier transform (FFT) under a single combinational fault model are presented. Initially, an unrestricted single cell-level fault model is considered. The first approach is based on a process whose complexity is independent of the number of cells in the FFT architecture. The second method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array. No additional hardware is required in this case. A component-level fault model is also proposed and analyzed.<>
{"title":"Testing constant-geometry FFT arrays for wafer scale integration","authors":"J. Salinas, C. Feng, F. Lombardi","doi":"10.1109/ICWSI.1993.255258","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255258","url":null,"abstract":"Two approaches for testing constant-geometry wafer scale integration (WSI) array architectures used in the computation of the complex N-point fast Fourier transform (FFT) under a single combinational fault model are presented. Initially, an unrestricted single cell-level fault model is considered. The first approach is based on a process whose complexity is independent of the number of cells in the FFT architecture. The second method is based on a testing process whose complexity is linear with respect to the number of stages (columns) of the FFT array. No additional hardware is required in this case. A component-level fault model is also proposed and analyzed.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114207442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255276
R. Berger, R. Frankel, J. Raffel, C. Woodward, P. Wyatt
A laser-programmable substrate for multichip modules comprises a silicon substrate with a dense, predefined array of pads, tracks and links. A pattern of wiring connecting some of the pads is formed with a laser. Integrated circuit chips are mounted on the substrate, and the chip pads are wire-bonded to the substrate pads. East-west tracks are on the second level of metal, and north-south tracks on the first level. Power, ground, and signals share the tracks on the two metal layers. There is an array of 258-by-258 pads on a 200- mu m pitch, and there are three signal tracks, one power track, and one ground track between any two adjacent pads. Links consist of a silicon nitride layer sandwiched between the two metal layers. When a laser pulse of the correct power and duration is directed to the link region, the metal and nitride fuse to form a conductive vertical path, with a resistance typically two ohms.<>
{"title":"A laser-programmable multichip module on silicon","authors":"R. Berger, R. Frankel, J. Raffel, C. Woodward, P. Wyatt","doi":"10.1109/ICWSI.1993.255276","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255276","url":null,"abstract":"A laser-programmable substrate for multichip modules comprises a silicon substrate with a dense, predefined array of pads, tracks and links. A pattern of wiring connecting some of the pads is formed with a laser. Integrated circuit chips are mounted on the substrate, and the chip pads are wire-bonded to the substrate pads. East-west tracks are on the second level of metal, and north-south tracks on the first level. Power, ground, and signals share the tracks on the two metal layers. There is an array of 258-by-258 pads on a 200- mu m pitch, and there are three signal tracks, one power track, and one ground track between any two adjacent pads. Links consist of a silicon nitride layer sandwiched between the two metal layers. When a laser pulse of the correct power and duration is directed to the link region, the metal and nitride fuse to form a conductive vertical path, with a resistance typically two ohms.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127902994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255268
C. Habiger, R. Lea
Hybrid wafer scale integration (HWSI) is a promising technology for the cost-effective development of the next generation of massively parallel computers (MPCs). It is argued that it is not easy to understand the relative merits and technological tradeoffs associated with vendor-specific factors in order to determine the best technological route for a particular application. Cost models aimed at the resolution of these problems are introduced, and progress towards a design methodology for HWSI devices is reported.<>
{"title":"Cost modelling for hybrid-WSI massively parallel computing modules","authors":"C. Habiger, R. Lea","doi":"10.1109/ICWSI.1993.255268","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255268","url":null,"abstract":"Hybrid wafer scale integration (HWSI) is a promising technology for the cost-effective development of the next generation of massively parallel computers (MPCs). It is argued that it is not easy to understand the relative merits and technological tradeoffs associated with vendor-specific factors in order to determine the best technological route for a particular application. Cost models aimed at the resolution of these problems are introduced, and progress towards a design methodology for HWSI devices is reported.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134542429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255252
M. Sriram, S.M. Kang
An algorithm for performance-driven routing is presented. It is based on a new second-order propagation delay model for RLC interconnection trees, which is more suitable than the Elmore time-constant model. Experimental results show that by using the new delay model instead of the first-order model, the performance-driven routing algorithm can generate routing with significantly smaller signal delays.<>
{"title":"Performance driven MCM routing using a second order RLC tree delay model","authors":"M. Sriram, S.M. Kang","doi":"10.1109/ICWSI.1993.255252","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255252","url":null,"abstract":"An algorithm for performance-driven routing is presented. It is based on a new second-order propagation delay model for RLC interconnection trees, which is more suitable than the Elmore time-constant model. Experimental results show that by using the new delay model instead of the first-order model, the performance-driven routing algorithm can generate routing with significantly smaller signal delays.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128739380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-01-20DOI: 10.1109/ICWSI.1993.255249
H. Stopper
The electrically programmable interconnection wafer for hybrid wafer scale integration (WSI) or multichip modules (MCMs) depends on three key constituents, which are the antifuse, the thin-film transmission line, and the architecture. Their impact on device performance is explored, and their parametric improvements from early to present and potential future devices are appraised.<>
{"title":"An advanced version of the electrically programmable hybrid-WSI substrate","authors":"H. Stopper","doi":"10.1109/ICWSI.1993.255249","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255249","url":null,"abstract":"The electrically programmable interconnection wafer for hybrid wafer scale integration (WSI) or multichip modules (MCMs) depends on three key constituents, which are the antifuse, the thin-film transmission line, and the architecture. Their impact on device performance is explored, and their parametric improvements from early to present and potential future devices are appraised.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130079337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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