Algorithmic bus and circuit layout for wafer-scale integration and multichip modules

G. Chapman, R. Hobson
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引用次数: 1

Abstract

In both laser-link-oriented wafer scale integration (WSI) and multichip modules (MCMs), arrays of devices may be ordered in such a way that the actual physical position of devices is extremely important. Traditional graphic-based design systems are not well suited for such applications. Examples are presented illustrating the effectiveness of a C-based design language (CDL) for WSI laser-link bus placement and MCM chip placement and interconnection. A brief description of the CDL platform is included.<>
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圆片级集成和多芯片模块的算法总线和电路布局
在面向激光链路的晶圆规模集成(WSI)和多芯片模块(mcm)中,器件阵列的排序方式可能使得器件的实际物理位置极其重要。传统的基于图形的设计系统并不适合这样的应用。举例说明了基于c语言的设计语言(CDL)在WSI激光链路总线放置和MCM芯片放置和互连方面的有效性。本文包含了对CDL平台的简要描述。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Testing constant-geometry FFT arrays for wafer scale integration Use of high dielectric constant insulators for bypass capacitance in WSI and wafer scale hybrid multichip modules 3D wafer stack neurocomputing Algorithmic bus and circuit layout for wafer-scale integration and multichip modules Effect of communication delay on gracefully degradable WSI processor array performance
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