{"title":"Effect of communication delay on gracefully degradable WSI processor array performance","authors":"D. Landis, N. Nigam","doi":"10.1109/ICWSI.1993.255260","DOIUrl":null,"url":null,"abstract":"Online reconfiguration of wafer scale integration (WSI) processor arrays provides graceful degradation of performance in the presence of failed processors. Each time a processor fails, soft switching can be used to bypass either a row or column and a degraded performance functional array can be maintained. Processor to processor communication delay may increase with each processor failure, and the entire array will eventually fail if the delay exceeds a predetermined limit. The impact of reconfiguration on fault tolerant WSI processor array performance is examined. The analysis considers interconnect length, communication delay, and maximum operating frequency.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1993.255260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Online reconfiguration of wafer scale integration (WSI) processor arrays provides graceful degradation of performance in the presence of failed processors. Each time a processor fails, soft switching can be used to bypass either a row or column and a degraded performance functional array can be maintained. Processor to processor communication delay may increase with each processor failure, and the entire array will eventually fail if the delay exceeds a predetermined limit. The impact of reconfiguration on fault tolerant WSI processor array performance is examined. The analysis considers interconnect length, communication delay, and maximum operating frequency.<>
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