D. Sekar, B. Bateman, U. Raghuram, S. Bowyer, Y. Bai, M. Calarrudo, P. Swab, J. Wu, S. Nguyen, N. Mishra, R. Meyer, M. Kellam, B. Haukness, C. Chevallier, H. Wu, H. Qian, F. Kreupl, G. Bronner
{"title":"Technology and circuit optimization of resistive RAM for low-power, reproducible operation","authors":"D. Sekar, B. Bateman, U. Raghuram, S. Bowyer, Y. Bai, M. Calarrudo, P. Swab, J. Wu, S. Nguyen, N. Mishra, R. Meyer, M. Kellam, B. Haukness, C. Chevallier, H. Wu, H. Qian, F. Kreupl, G. Bronner","doi":"10.1109/IEDM.2014.7047125","DOIUrl":null,"url":null,"abstract":"Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaOx/HfO2/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2014.7047125","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
Low-power, reproducible operation of Resistive RAM (RRAM) requires control of capacitive surge currents during write. We propose a fab-friendly TiN/conductive TaOx/HfO2/TiN RRAM with a built-in surge current reduction layer. It reduces worst case write current by 33% and fail bit count by 23× compared to conventional RRAM. A novel circuit to control surge current is demonstrated that improves write current by 40% and endurance by 63%. Switching, endurance and retention data for a 256kb chip with these concepts is presented.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
