Pub Date : 2014-12-15DOI: 10.1109/IEDM.2014.7047166
J. Ma, W. Zhang, J. F. Zhang, B. Benbakhti, Z. Ji, J. Mitard, J. Franco, B. Kaczer, G. Groeseneken
Conventional lifetime prediction method developed for Si is inapplicable to Ge devices. This work demonstrates that the defects are different in Ge and Si devices. Based on the investigation of defect difference, for the first time, a method is developed for Ge devices to restore the power law for NBTI kinetics, enabling lifetime prediction. This method is applicable for both GeO2/Ge and Sicap/Ge devices, assisting in further Ge process/device optimization.
{"title":"NBTI of Ge pMOSFETs: Understanding defects and enabling lifetime prediction","authors":"J. Ma, W. Zhang, J. F. Zhang, B. Benbakhti, Z. Ji, J. Mitard, J. Franco, B. Kaczer, G. Groeseneken","doi":"10.1109/IEDM.2014.7047166","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047166","url":null,"abstract":"Conventional lifetime prediction method developed for Si is inapplicable to Ge devices. This work demonstrates that the defects are different in Ge and Si devices. Based on the investigation of defect difference, for the first time, a method is developed for Ge devices to restore the power law for NBTI kinetics, enabling lifetime prediction. This method is applicable for both GeO2/Ge and Sicap/Ge devices, assisting in further Ge process/device optimization.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129659565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047130
N. Xu, Jeff Sun, I. Chen, L. Hutin, Yenhao Chen, J. Fujiki, Chuang Qian, T. Liu
Three-dimensional (3-D) nano-electro-mechanical (NEM) switches (relays) are proposed to reduce the die area and power consumption of digital logic and memory circuits.
为了减少数字逻辑与存储电路的芯片面积和功耗，提出了三维纳米机电开关(继电器)。
{"title":"Hybrid CMOS/BEOL-NEMS technology for ultra-low-power IC applications","authors":"N. Xu, Jeff Sun, I. Chen, L. Hutin, Yenhao Chen, J. Fujiki, Chuang Qian, T. Liu","doi":"10.1109/IEDM.2014.7047130","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047130","url":null,"abstract":"Three-dimensional (3-D) nano-electro-mechanical (NEM) switches (relays) are proposed to reduce the die area and power consumption of digital logic and memory circuits.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115295336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047082
K. Tsunoda, M. Aoki, H. Noshiro, Y. Iba, S. Fukuda, C. Yoshida, Y. Yamazaki, A. Takahashi, A. Hatada, M. Nakabayashi, Y. Tsuzaki, T. Sugii
We report a statistical analysis of the thermal stability factor (Δ) for the top-pinned perpendicular magnetic tunnel junction (p-MTJ). By using a bi-directional data flipping model, the data retention characteristics of the “0” and “1” states can be fitted separately, including the saturation of failure probability. With the help of a resistance evaluation for the 16-kbit MTJ array, it became clear that the Δ of the “1” state increased as the device area increased, whereas the Δ of the “0” state remains constant regardless of the size. Moreover, we found that the p-MTJ exhibited a much smaller variation of Δ (9.6 ~ 14.3%) compared with the in-plane MTJ. Variations of Δ in both states decreased as the area increased. In combination with an intense magnetic measurement for the discrete monitor devices, the key parameter to increase the Δ and suppress its variation was investigated.
{"title":"Area dependence of thermal stability factor in perpendicular STT-MRAM analyzed by bi-directional data flipping model","authors":"K. Tsunoda, M. Aoki, H. Noshiro, Y. Iba, S. Fukuda, C. Yoshida, Y. Yamazaki, A. Takahashi, A. Hatada, M. Nakabayashi, Y. Tsuzaki, T. Sugii","doi":"10.1109/IEDM.2014.7047082","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047082","url":null,"abstract":"We report a statistical analysis of the thermal stability factor (Δ) for the top-pinned perpendicular magnetic tunnel junction (p-MTJ). By using a bi-directional data flipping model, the data retention characteristics of the “0” and “1” states can be fitted separately, including the saturation of failure probability. With the help of a resistance evaluation for the 16-kbit MTJ array, it became clear that the Δ of the “1” state increased as the device area increased, whereas the Δ of the “0” state remains constant regardless of the size. Moreover, we found that the p-MTJ exhibited a much smaller variation of Δ (9.6 ~ 14.3%) compared with the in-plane MTJ. Variations of Δ in both states decreased as the area increased. In combination with an intense magnetic measurement for the discrete monitor devices, the key parameter to increase the Δ and suppress its variation was investigated.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125800992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047176
Z. Zong, Ling Li, Jin Jang, Zhigang Li, Nianduan Lu, Liwei Shang, Z. Ji, Ming Liu
For the first time, we present a surface potential-based compact model for a-IGZO TFTs based on multiple trapping-release theory and benchmark our work against device measurements. This model does not require time-consuming calculation. Meanwhile, we have developed the automatic parameter extraction program, which can extract the parameters rapidly and accurately. Moreover, the compact model is coded in Verilog-A, and implemented in a vendor CAD environment. This model provides physics-based consistent description of DC and AC device characteristics and enables accurate circuit-level performance prediction and RFID circuit design of a-IGZO TFTs.
{"title":"A new surface potential-based compact model for a-IGZO TFTs in RFID applications","authors":"Z. Zong, Ling Li, Jin Jang, Zhigang Li, Nianduan Lu, Liwei Shang, Z. Ji, Ming Liu","doi":"10.1109/IEDM.2014.7047176","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047176","url":null,"abstract":"For the first time, we present a surface potential-based compact model for a-IGZO TFTs based on multiple trapping-release theory and benchmark our work against device measurements. This model does not require time-consuming calculation. Meanwhile, we have developed the automatic parameter extraction program, which can extract the parameters rapidly and accurately. Moreover, the compact model is coded in Verilog-A, and implemented in a vendor CAD environment. This model provides physics-based consistent description of DC and AC device characteristics and enables accurate circuit-level performance prediction and RFID circuit design of a-IGZO TFTs.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125818802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7046965
R. Rupp, T. Laska, O. Haberlen, M. Treu
There is an increasing choice of power switches in the 600V to 1700V range for the application engineers. Besides the well-established Si SJ (Super Junction) MOSFETs and IGBTs now also silicon carbide (SiC) and latest gallium nitride (GaN) power switches are available for new designs. Complete new system optimizations are possible driven by totally different trade off options e.g. between static and dynamic losses and their temperature dependencies. In this paper we explain these trade-offs for the different device types and show the consequences based on some prominent sample applications.
{"title":"Application specific trade-offs for WBG SiC, GaN and high end Si power switch technologies","authors":"R. Rupp, T. Laska, O. Haberlen, M. Treu","doi":"10.1109/IEDM.2014.7046965","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046965","url":null,"abstract":"There is an increasing choice of power switches in the 600V to 1700V range for the application engineers. Besides the well-established Si SJ (Super Junction) MOSFETs and IGBTs now also silicon carbide (SiC) and latest gallium nitride (GaN) power switches are available for new designs. Complete new system optimizations are possible driven by totally different trade off options e.g. between static and dynamic losses and their temperature dependencies. In this paper we explain these trade-offs for the different device types and show the consequences based on some prominent sample applications.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125436563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047129
N. Shukla, A. Parihar, M. Cotter, M. Barth, Xueqing Li, Nandhini Chandramoorthy, H. Paik, D. Schlom, V. Narayanan, A. Raychowdhury, Suman Datta
Information processing applications related to associative computing like image / pattern recognition consume excessive computational resources in the Boolean processing framework. This motivates the exploration of a non-Boolean computing approach for such applications. In this work, we demonstrate, (i) novel hybrid set of pair-wise coupled oscillators comprising of vanadium dioxide (VO2) metal-insulator-transition (MIT) system integrated with MOSFET; (ii) degree of synchronization between oscillators based on input analog voltage difference; (iii) implementation of hardware platform for fast and efficient evaluation of Lk fractional distance norm (k<;1); (iv) improved quality of image processing and ~20X lower power consumption of the coupled oscillators over a CMOS accelerator.
{"title":"Pairwise coupled hybrid vanadium dioxide-MOSFET (HVFET) oscillators for non-boolean associative computing","authors":"N. Shukla, A. Parihar, M. Cotter, M. Barth, Xueqing Li, Nandhini Chandramoorthy, H. Paik, D. Schlom, V. Narayanan, A. Raychowdhury, Suman Datta","doi":"10.1109/IEDM.2014.7047129","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047129","url":null,"abstract":"Information processing applications related to associative computing like image / pattern recognition consume excessive computational resources in the Boolean processing framework. This motivates the exploration of a non-Boolean computing approach for such applications. In this work, we demonstrate, (i) novel hybrid set of pair-wise coupled oscillators comprising of vanadium dioxide (VO2) metal-insulator-transition (MIT) system integrated with MOSFET; (ii) degree of synchronization between oscillators based on input analog voltage difference; (iii) implementation of hardware platform for fast and efficient evaluation of Lk fractional distance norm (k<;1); (iv) improved quality of image processing and ~20X lower power consumption of the coupled oscillators over a CMOS accelerator.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"18 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126719643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7046979
N. Ahmed, F. Roy, G. Lu, B. Mamdy, J. Carrere, A. Tournier, N. Virollet, C. Perrot, M. Rivoire, A. Seignard, D. Pellissier-Tanon, F. Leverd, B. Orlando
This paper proposes the integration of MOS Capacitor Deep Trench Isolation (CDTI) as a solution to boost image sensors' pixels performances. We have investigated CDTI and compared it to oxide-filled Deep Trench Isolation (DTI) configurations, on silicon samples, with a fabrication based on TCAD simulations. The experiment measurements evaluated on CDTI without Sidewall Implantation (SWI) exhibit very low dark current (~1aA at 60°C for a 1.4μm pixel), high full-well capacity (~12000e-), and it shows quantum efficiency improvement compared to DTI configuration. Pixels with optimized CDTI gate oxide thickness have demonstrated comparable angular response to oxide-filled DTI counterparts.
{"title":"MOS Capacitor Deep Trench Isolation for CMOS image sensors","authors":"N. Ahmed, F. Roy, G. Lu, B. Mamdy, J. Carrere, A. Tournier, N. Virollet, C. Perrot, M. Rivoire, A. Seignard, D. Pellissier-Tanon, F. Leverd, B. Orlando","doi":"10.1109/IEDM.2014.7046979","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046979","url":null,"abstract":"This paper proposes the integration of MOS Capacitor Deep Trench Isolation (CDTI) as a solution to boost image sensors' pixels performances. We have investigated CDTI and compared it to oxide-filled Deep Trench Isolation (DTI) configurations, on silicon samples, with a fabrication based on TCAD simulations. The experiment measurements evaluated on CDTI without Sidewall Implantation (SWI) exhibit very low dark current (~1aA at 60°C for a 1.4μm pixel), high full-well capacity (~12000e-), and it shows quantum efficiency improvement compared to DTI configuration. Pixels with optimized CDTI gate oxide thickness have demonstrated comparable angular response to oxide-filled DTI counterparts.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122445458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047102
H. Campanella, Nan Wang, M. Narducci, J. Soon, C. Ho, Chengkuo Lee, A. Gu
We report a radio frequency micro electromechanical system (RFMEMS) device integrated with phononic crystals (PnC) that provide a Lamb-wave resonator with frequency-selective heat management, power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) and low microwave bands. The integrated device is fabricated in a silicon-on-insulator (SOI) aluminum nitride (AlN) platform and boosts thermal performance by 40%, power handling by 3 dB, and coupling coefficient by three times. Design approach is scalable to higher frequencies.
{"title":"Integration of RF MEMS resonators and phononic crystals for high frequency applications with frequency-selective heat management and efficient power handling","authors":"H. Campanella, Nan Wang, M. Narducci, J. Soon, C. Ho, Chengkuo Lee, A. Gu","doi":"10.1109/IEDM.2014.7047102","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047102","url":null,"abstract":"We report a radio frequency micro electromechanical system (RFMEMS) device integrated with phononic crystals (PnC) that provide a Lamb-wave resonator with frequency-selective heat management, power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) and low microwave bands. The integrated device is fabricated in a silicon-on-insulator (SOI) aluminum nitride (AlN) platform and boosts thermal performance by 40%, power handling by 3 dB, and coupling coefficient by three times. Design approach is scalable to higher frequencies.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122057527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7047170
Changze Liu, Kyongtaek Lee, S. Pae, Jongwoo Park
In this paper, HCI induced dynamic variation in nano-scaled MOSFETs is systematically studied. Based on the proposed on-the-fly HCI technique, individual defect related HCI variation in small area device is observed for the first time. The fundamental properties of HCI variation sources (single trap induced degradation and trap number) are further investigated. The results show universal scaling trend for all the SiON/Poly, HK/MG and FinFET devices which confirms that the device dimension scaling is the dominant factor for the enhanced individual trap effect. Based on the new observations, HCI variation model is further discussed for the accurate prediction for design. Moreover, HCI variation is compared with BTI and RTN in terms of individual trap. The results show that HCI effect has the largest single trap impacts, which implies the defects responsible for HCI could be closer to dielectric-silicon interface than that for BTI and RTN.
{"title":"New observations on hot carrier induced dynamic variation in nano-scaled SiON/poly, HK/MG and FinFET devices based on on-the-fly HCI technique: The role of single trap induced degradation","authors":"Changze Liu, Kyongtaek Lee, S. Pae, Jongwoo Park","doi":"10.1109/IEDM.2014.7047170","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047170","url":null,"abstract":"In this paper, HCI induced dynamic variation in nano-scaled MOSFETs is systematically studied. Based on the proposed on-the-fly HCI technique, individual defect related HCI variation in small area device is observed for the first time. The fundamental properties of HCI variation sources (single trap induced degradation and trap number) are further investigated. The results show universal scaling trend for all the SiON/Poly, HK/MG and FinFET devices which confirms that the device dimension scaling is the dominant factor for the enhanced individual trap effect. Based on the new observations, HCI variation model is further discussed for the accurate prediction for design. Moreover, HCI variation is compared with BTI and RTN in terms of individual trap. The results show that HCI effect has the largest single trap impacts, which implies the defects responsible for HCI could be closer to dielectric-silicon interface than that for BTI and RTN.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122125573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/IEDM.2014.7046997
J. Guy, G. Molas, P. Blaise, C. Carabasse, M. Bernard, A. Roule, G. Carval, Veronique Sousa, H. Grampeix, V. Delaye, A. Toffoli, J. Cluzel, P. Brianceau, O. Pollet, V. Balan, S. Barraud, O. Cueto, Gérard Ghibaudo, F. Clermidy, B. D. Salvo, L. Perniola
In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).
{"title":"Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization","authors":"J. Guy, G. Molas, P. Blaise, C. Carabasse, M. Bernard, A. Roule, G. Carval, Veronique Sousa, H. Grampeix, V. Delaye, A. Toffoli, J. Cluzel, P. Brianceau, O. Pollet, V. Balan, S. Barraud, O. Cueto, Gérard Ghibaudo, F. Clermidy, B. D. Salvo, L. Perniola","doi":"10.1109/IEDM.2014.7046997","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046997","url":null,"abstract":"In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128306858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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