Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies

Abstract

Small delay defects caused by resistive opens are very common in nanometer technologies due to the rising number of vias and metal levels. The detection of this kind of defects is a major concern in modern circuits. These defects are hard to detect and are an important source of test escapes, and hence they represent a reliability risk. Furthermore, the detection of these defects aggravates in the presence of process variations and gets worse as the technology scales-down. In this paper, a Design-for-Test (DFT) methodology to magnify the defect-size of resistive-open defects is presented. The DFT methodology allows to increase the probability of detection of the defect, and hence the circuit fault coverage. A statistical timing analysis framework (STAF) is used to obtain the timing information of the circuit with and without defect. Process variations, spatial correlation and random dopant fluctuations are considered. Using the timing information given by the STAF, the statistical fault coverage of the circuit is obtained. Simulation results on ISCAS-85 benchmark circuits show promising results of the proposed DFT methodology.