Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841919
E. C. F. Pereira, O. Gonçalez, R. G. Vaz, C. Federico, T. H. Both, G. Wirth
Fast neutron single event upset (SEU) cross section of an 130 nm 4 Mb SRAM memory was measured by exposing the memory chip to a known quasi-isotropic fast neutron fluency from a radioactive 241Am-Be neutron source. The cross section measurements were performed after exposing the memory chip to three gamma-rays accumulated doses steps and it was observed a slight growing of the neutron SEU cross section according the total ionizing dose (TID).
{"title":"The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory","authors":"E. C. F. Pereira, O. Gonçalez, R. G. Vaz, C. Federico, T. H. Both, G. Wirth","doi":"10.1109/LATW.2014.6841919","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841919","url":null,"abstract":"Fast neutron single event upset (SEU) cross section of an 130 nm 4 Mb SRAM memory was measured by exposing the memory chip to a known quasi-isotropic fast neutron fluency from a radioactive 241Am-Be neutron source. The cross section measurements were performed after exposing the memory chip to three gamma-rays accumulated doses steps and it was observed a slight growing of the neutron SEU cross section according the total ionizing dose (TID).","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127182475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841916
I. A. C. Gomes, Mayler G. A. Martins, F. Kastensmidt, A. Reis, R. Ribas, Sylvain P. Novales
The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults. However, it presents a minimum area overhead of 200% compared to the original circuit. In order to reduce area overhead without compromising significantly the fault coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized in area compared to the original module. Initial studies of this technique have shown that it is possible to reach a good balance between fault coverage and area overhead cost. In this work, we do a further analysis of this approach by using a new method to compute approximate functions and to select the best combinations of approximate circuits targeting the highest fault coverage. We use complex gates and employ structural reorder techniques. All the tests are done using a fault injection tool designed specifically for approximate TMR scheme. Results show that area overhead can be reduced greatly from 200% to 120%and still reaching fault coverage of more than 95%.
{"title":"Methodology for achieving best trade-off of area and fault masking coverage in ATMR","authors":"I. A. C. Gomes, Mayler G. A. Martins, F. Kastensmidt, A. Reis, R. Ribas, Sylvain P. Novales","doi":"10.1109/LATW.2014.6841916","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841916","url":null,"abstract":"The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults. However, it presents a minimum area overhead of 200% compared to the original circuit. In order to reduce area overhead without compromising significantly the fault coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized in area compared to the original module. Initial studies of this technique have shown that it is possible to reach a good balance between fault coverage and area overhead cost. In this work, we do a further analysis of this approach by using a new method to compute approximate functions and to select the best combinations of approximate circuits targeting the highest fault coverage. We use complex gates and employ structural reorder techniques. All the tests are done using a fault injection tool designed specifically for approximate TMR scheme. Results show that area overhead can be reduced greatly from 200% to 120%and still reaching fault coverage of more than 95%.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123858951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841909
J. L. Garcia-Gervacio, J. Martínez-Castillo, V. Champac
Small delay defects caused by resistive opens are very common in nanometer technologies due to the rising number of vias and metal levels. The detection of this kind of defects is a major concern in modern circuits. These defects are hard to detect and are an important source of test escapes, and hence they represent a reliability risk. Furthermore, the detection of these defects aggravates in the presence of process variations and gets worse as the technology scales-down. In this paper, a Design-for-Test (DFT) methodology to magnify the defect-size of resistive-open defects is presented. The DFT methodology allows to increase the probability of detection of the defect, and hence the circuit fault coverage. A statistical timing analysis framework (STAF) is used to obtain the timing information of the circuit with and without defect. Process variations, spatial correlation and random dopant fluctuations are considered. Using the timing information given by the STAF, the statistical fault coverage of the circuit is obtained. Simulation results on ISCAS-85 benchmark circuits show promising results of the proposed DFT methodology.
{"title":"Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies","authors":"J. L. Garcia-Gervacio, J. Martínez-Castillo, V. Champac","doi":"10.1109/LATW.2014.6841909","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841909","url":null,"abstract":"Small delay defects caused by resistive opens are very common in nanometer technologies due to the rising number of vias and metal levels. The detection of this kind of defects is a major concern in modern circuits. These defects are hard to detect and are an important source of test escapes, and hence they represent a reliability risk. Furthermore, the detection of these defects aggravates in the presence of process variations and gets worse as the technology scales-down. In this paper, a Design-for-Test (DFT) methodology to magnify the defect-size of resistive-open defects is presented. The DFT methodology allows to increase the probability of detection of the defect, and hence the circuit fault coverage. A statistical timing analysis framework (STAF) is used to obtain the timing information of the circuit with and without defect. Process variations, spatial correlation and random dopant fluctuations are considered. Using the timing information given by the STAF, the statistical fault coverage of the circuit is obtained. Simulation results on ISCAS-85 benchmark circuits show promising results of the proposed DFT methodology.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114878494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841912
V. Martins, Frederico Ferlini, D. Lettnin, E. Bezerra
Field Programmable Gate Arrays (FPGAs), as any other electronic devices, are designed according to some life expectancy figures. For this reason, its lifetime is finite given due to appearance of faults caused by the natural physical degradation. In this paper, we present a low cost solution for autonomous detection of faults at the end of FPGAs life cycle. Our proposed methodology starts from a pre-analysis of memory elements belonging to modules under verification. Then, with a proper organization, it is created a list of all memory elements, controlled through a Built-In Self-Test (BIST) implementation via the FPGAs Internal Configuration Access Port (ICAP). By means of this list, a virtual scan chain is created, where the vectors (test and result) are written and read using the FPGA reconfiguration capabilities, which means there is no extra hardware to create the physical scan chain. The detection algorithm is implemented in the available system processing unit. The results show that with a minor increase in the program memory of the digital design, it is possible to perform an offline hardware testing of each sub-module in the existing FPGA, with no need of stopping the remaining of the system.
{"title":"Low cost fault detector guided by permanent faults at the end of FPGAs life cycle","authors":"V. Martins, Frederico Ferlini, D. Lettnin, E. Bezerra","doi":"10.1109/LATW.2014.6841912","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841912","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs), as any other electronic devices, are designed according to some life expectancy figures. For this reason, its lifetime is finite given due to appearance of faults caused by the natural physical degradation. In this paper, we present a low cost solution for autonomous detection of faults at the end of FPGAs life cycle. Our proposed methodology starts from a pre-analysis of memory elements belonging to modules under verification. Then, with a proper organization, it is created a list of all memory elements, controlled through a Built-In Self-Test (BIST) implementation via the FPGAs Internal Configuration Access Port (ICAP). By means of this list, a virtual scan chain is created, where the vectors (test and result) are written and read using the FPGA reconfiguration capabilities, which means there is no extra hardware to create the physical scan chain. The detection algorithm is implemented in the available system processing unit. The results show that with a minor increase in the program memory of the digital design, it is possible to perform an offline hardware testing of each sub-module in the existing FPGA, with no need of stopping the remaining of the system.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"112 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131942169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841920
L. Tambara, Jorge Tonfat, R. Reis, F. Kastensmidt, E. C. F. Pereira, R. G. Vaz, O. Gonçalez
This paper presents new experimental results about the sensitivity of an SRAM-based FPGA under neutron-induced and total ionizing dose effects. Both effects are combined in a practical experiment composed of a set of eight isotropic emission material blocks for neutron irradiation and a gamma rays source for ionizing dose. The experiment was performed at Instituto de Estudos Avançados, São José dos Campos, Brazil. The soft error rate has been measured from counting the bit-flip rate of the configuration memory bits and the errors at the output of the design application. Current results have shown that the soft error rate increases under neutrons when the accumulation of ionizing radiation in the device also increases until the observed doses.
{"title":"Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects","authors":"L. Tambara, Jorge Tonfat, R. Reis, F. Kastensmidt, E. C. F. Pereira, R. G. Vaz, O. Gonçalez","doi":"10.1109/LATW.2014.6841920","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841920","url":null,"abstract":"This paper presents new experimental results about the sensitivity of an SRAM-based FPGA under neutron-induced and total ionizing dose effects. Both effects are combined in a practical experiment composed of a set of eight isotropic emission material blocks for neutron irradiation and a gamma rays source for ionizing dose. The experiment was performed at Instituto de Estudos Avançados, São José dos Campos, Brazil. The soft error rate has been measured from counting the bit-flip rate of the configuration memory bits and the errors at the output of the design application. Current results have shown that the soft error rate increases under neutrons when the accumulation of ionizing radiation in the device also increases until the observed doses.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116549658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841908
A. J. C. Lanot, T. Balen
This work presents a study on the effects of Single Event Transients on SAR A/D converters based on charge redistribution. The effects of SETs are analyzed considering the worst-case pulses for the 130nm CMOS process. In this work, the fault injection is concentrated on the switches of the capacitor array of the studied converter. Preliminary results show that the transient effects may change the state of one or more bits of conversion. This is due the fact that the affected stage may propagate an incorrect value to the remainder of the conversion, leading to multiple bit errors on the converted data. Moreover, a SET occurring on the switch connected to the common node of the capacitors may lead to an incorrect behavior that cannot be attenuated with the increasing on the sizing of the transistors, which suggests that additional fault tolerance techniques may be needed.
本文研究了单事件瞬态对基于电荷再分配的SAR a /D变换器的影响。针对130nm CMOS工艺的最坏情况，分析了set的影响。在本工作中，故障注入主要集中在所研究的变换器的电容阵列开关上。初步结果表明，瞬态效应可能改变一个或多个转换位的状态。这是由于受影响的阶段可能会将不正确的值传播到转换的其余部分，从而导致转换数据上的多个位错误。此外，在连接到电容器公共节点的开关上发生的SET可能导致不正确的行为，这种行为不能随着晶体管尺寸的增加而衰减，这表明可能需要额外的容错技术。
{"title":"Analysis of the effects of single event transients on an SAR-ADC based on charge redistribution","authors":"A. J. C. Lanot, T. Balen","doi":"10.1109/LATW.2014.6841908","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841908","url":null,"abstract":"This work presents a study on the effects of Single Event Transients on SAR A/D converters based on charge redistribution. The effects of SETs are analyzed considering the worst-case pulses for the 130nm CMOS process. In this work, the fault injection is concentrated on the switches of the capacitor array of the studied converter. Preliminary results show that the transient effects may change the state of one or more bits of conversion. This is due the fact that the affected stage may propagate an incorrect value to the remainder of the conversion, leading to multiple bit errors on the converted data. Moreover, a SET occurring on the switch connected to the common node of the capacitors may lead to an incorrect behavior that cannot be attenuated with the increasing on the sizing of the transistors, which suggests that additional fault tolerance techniques may be needed.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116533719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841921
A. Rossetto, G. Wirth, Ricardo Vanni Dallasen
Phase-Locked Loops (PLLs) are widely used as frequency synthesizers for clock signal generation. In aerospace environment, however, the performance of the PLL can be degraded due to the radiation exposure, which causes degradation of the parameters of its components. Thereby, this article presents a performance analysis of a clock generator PLL under TID effects. Output frequency, power consumption and control voltage variations are analyzed for different accumulated doses and compared with normal operating results, evidencing the performance degradation. PLL functional failures were also observed and discussed. The circuit was designed in a 0.35μm CMOS process and the simulations were performed using HSPICE simulator.
{"title":"Performance analysis of a clock generator PLL under TID effects","authors":"A. Rossetto, G. Wirth, Ricardo Vanni Dallasen","doi":"10.1109/LATW.2014.6841921","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841921","url":null,"abstract":"Phase-Locked Loops (PLLs) are widely used as frequency synthesizers for clock signal generation. In aerospace environment, however, the performance of the PLL can be degraded due to the radiation exposure, which causes degradation of the parameters of its components. Thereby, this article presents a performance analysis of a clock generator PLL under TID effects. Output frequency, power consumption and control voltage variations are analyzed for different accumulated doses and compared with normal operating results, evidencing the performance degradation. PLL functional failures were also observed and discussed. The circuit was designed in a 0.35μm CMOS process and the simulations were performed using HSPICE simulator.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122854993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841923
R. Ubar, A. Tsertov, Artjom Jasnetski, M. Brik
Software-based self-testing (SBST) is a well known non-intrusive method for processor testing. Its applications have been intensively studied by the research community for the last decades. Generally, the inextinguishable attention to this method is mainly caused by continuous growth of complexity of modern processors that poses new research challenges. One of these challenges is automated generation of software-based self-tests. Through the years the main research trend was focused on reducing the processor representation complexity by shifting the modeling process towards more general abstraction layers. This paper presents the approach for high-level processor modeling, which is the next convolution of SBST methodology. We propose the methodology for processor modeling at behavioral level that can be used for automatic generation of SBST programs. The method leads to significant complexity reduction compared to RT-level and as experimental results show the efficiency of SBST in terms of fault coverage is not compromised in comparison to state-of-the-art SBST approaches.
{"title":"Software-based self-test generation for microprocessors with high-level decision diagrams","authors":"R. Ubar, A. Tsertov, Artjom Jasnetski, M. Brik","doi":"10.1109/LATW.2014.6841923","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841923","url":null,"abstract":"Software-based self-testing (SBST) is a well known non-intrusive method for processor testing. Its applications have been intensively studied by the research community for the last decades. Generally, the inextinguishable attention to this method is mainly caused by continuous growth of complexity of modern processors that poses new research challenges. One of these challenges is automated generation of software-based self-tests. Through the years the main research trend was focused on reducing the processor representation complexity by shifting the modeling process towards more general abstraction layers. This paper presents the approach for high-level processor modeling, which is the next convolution of SBST methodology. We propose the methodology for processor modeling at behavioral level that can be used for automatic generation of SBST programs. The method leads to significant complexity reduction compared to RT-level and as experimental results show the efficiency of SBST in terms of fault coverage is not compromised in comparison to state-of-the-art SBST approaches.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117076670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841929
S. Krit, W. Rahajandraibe, K. Castellani-Coulié, G. Micolau, A. Levisse, A. Lyoussi
The development of a digital tool dedicated for the test and the simulation of a reading system for neutron detection is presented. This study takes place in the framework of the I_SMART* European project. This system will have to work in harsh environment in terms of temperature and radiations what makes necessary the development of specifications for operation and reliability of the components and also the investigation of margins of interplay of the components. The specifications of the implemented tool are presented here with the different results of simulation related to the input designed parameters of the readout system.
{"title":"Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination","authors":"S. Krit, W. Rahajandraibe, K. Castellani-Coulié, G. Micolau, A. Levisse, A. Lyoussi","doi":"10.1109/LATW.2014.6841929","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841929","url":null,"abstract":"The development of a digital tool dedicated for the test and the simulation of a reading system for neutron detection is presented. This study takes place in the framework of the I_SMART* European project. This system will have to work in harsh environment in terms of temperature and radiations what makes necessary the development of specifications for operation and reliability of the components and also the investigation of margins of interplay of the components. The specifications of the implemented tool are presented here with the different results of simulation related to the input designed parameters of the readout system.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126194162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841899
Shih-Yi Yuan
Electronic products are now essential to daily lives. Although power-saving are well known for consumers, electromagnetic compatibility (EMC) issues are the most critical issues which determine the pass/fail criteria of electronic products coming into the market. Since modern software can control almost any device hardware features and EMC is just one of them, software is capable of controlling it. Thus, software-related EMC for modern digital systems is essential for all electronic products. This paper is a modest attempt to review key developments that mark the history and recent progress in the software-related EMC researches.
{"title":"Recent progress of software-related electromagnetic compatibility","authors":"Shih-Yi Yuan","doi":"10.1109/LATW.2014.6841899","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841899","url":null,"abstract":"Electronic products are now essential to daily lives. Although power-saving are well known for consumers, electromagnetic compatibility (EMC) issues are the most critical issues which determine the pass/fail criteria of electronic products coming into the market. Since modern software can control almost any device hardware features and EMC is just one of them, software is capable of controlling it. Thus, software-related EMC for modern digital systems is essential for all electronic products. This paper is a modest attempt to review key developments that mark the history and recent progress in the software-related EMC researches.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121709994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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