Designing a memory module tester

D.P. van der Velde, A.J. v.d. Goor
{"title":"Designing a memory module tester","authors":"D.P. van der Velde, A.J. v.d. Goor","doi":"10.1109/MTDT.1999.782689","DOIUrl":null,"url":null,"abstract":"In the manufacturing process of memory modules (such as SIMMs and DIMMs), first memories are tested at the die level, then at the chip level, and finally at the module level. For the latter special module testers are available. This paper gives an analysis of commercially available module testers and shows their restrictions. Then it lists the requirements for a more advanced module tester, after which a complete functional design is given. The result is a very flexible tester capable of testing FPM/EDO and SDRAM memories, programmable using Texas Instruments TMS320C6201 DSPs and Vantis CPLDs, with an expected end-user price of less than US$ 20,000.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1999.782689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

In the manufacturing process of memory modules (such as SIMMs and DIMMs), first memories are tested at the die level, then at the chip level, and finally at the module level. For the latter special module testers are available. This paper gives an analysis of commercially available module testers and shows their restrictions. Then it lists the requirements for a more advanced module tester, after which a complete functional design is given. The result is a very flexible tester capable of testing FPM/EDO and SDRAM memories, programmable using Texas Instruments TMS320C6201 DSPs and Vantis CPLDs, with an expected end-user price of less than US$ 20,000.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
设计一个内存模块测试器
在内存模块(如simm和dimm)的制造过程中,首先在芯片级测试内存,然后在芯片级测试内存,最后在模块级测试内存。对于后者,可以使用专用模块测试仪。本文对市面上现有的模块测试仪进行了分析,并指出了它们的局限性。然后列出了一个更高级的模块测试仪的需求,然后给出了完整的功能设计。结果是一个非常灵活的测试仪,能够测试FPM/EDO和SDRAM存储器,使用德州仪器TMS320C6201 dsp和Vantis cpld进行编程,预计最终用户价格低于20,000美元。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Design validation of .18 /spl mu/m 1 GHz cache and register arrays A tribute to graphics DRAMs Computing in memory architectures for digital image processing Tutorial: characterizing SDRAMs Interconnect diagnosis of bus-connected multi-RAM systems
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1