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Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing最新文献

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A tribute to graphics DRAMs 向图形dram致敬
B. Prince
High speed graphics subsystems used some of the earliest application specific DRAMs. Knowledge gained from working with these specialized parts has provided a background for many of the innovations seen today in high speed DRAMs, fast core DRAMs, and high bandwidth embedded DRAMs. Years before synchronous DRAMs become common, clocked DRAM field memories for television frame buffers were in production. The later Video DRAMs were precursors for EDO page mode, dual bank architecture, synchronous operation, and high bandwidth through use of a wide internal bus. Implementations for graphics subsystems today continue to spearhead the emerging area of embedded DRAMs and parallel processing.
高速图形子系统使用了一些最早的专用dram。从这些专业部件的工作中获得的知识为今天在高速dram,快速核心dram和高带宽嵌入式dram中看到的许多创新提供了背景。在同步DRAM普及的几年前,用于电视帧缓冲的定时DRAM现场存储器已经开始生产。后来的视频dram是EDO页面模式、双银行架构、同步操作和通过使用宽内部总线实现高带宽的先驱。今天图形子系统的实现继续引领嵌入式dram和并行处理的新兴领域。
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引用次数: 2
Low-power SRAM circuit design 低功耗SRAM电路设计
M. Margala
This paper presents an extensive summary of the latest developments in low-power circuit techniques and methods for Static Random Access Memories. The key techniques in power reduction in both active and standby modes are: capacitance reduction by using divided word-line structure or single-bitline cross-point cell activation, pulse operation by using ATD generator and reduced signal swings on high-capacitance predecode lines, write bus lines and datalines, AC current reduction by using multistage decoding, operating voltage reduction coupled with low-power sensing by using charge-transfer amplification, step-down boosted word-line scheme or full current-mode read/write operation and leakage current suppression by using dual-Vt, Auto-Backgate-Controlled multiple-Vt, or dynamic leakage cut-off techniques.
本文对静态随机存储器的低功耗电路技术和方法的最新进展进行了广泛的总结。在活动和待机模式下降低功耗的关键技术是:采用分字线结构或单位线交叉点单元激活来减小电容;采用ATD发生器进行脉冲操作并减小高电容前置线、写母线和数据线上的信号波动;采用多级解码来减小交流电流;降压增强字线方案或全电流模式读/写操作,并通过使用双电压、自动后门控制多电压或动态泄漏截止技术抑制泄漏电流。
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引用次数: 57
The potential of carbon-based memory systems 碳基存储系统的潜力
Mark Brehob, R. Enbody
It seems likely that density concerns will force the DRAM community to consider using radically different schemes for the implementation of memory devices. We propose using nano-scale carbon structures as the basis for a memory device. A single-wall carbon nanotube would contain a charged buckyball. That buckyball will stick tightly to one end of the tube or the other. We assign the bit value of the device depending on which side of the tube the ball is. The result is a high-speed, non-volatile bit of memory. We propose a number of schemes for the interconnection of these devices and examine some of the known electrical issues.
似乎密度问题将迫使DRAM社区考虑使用完全不同的方案来实现存储器设备。我们建议使用纳米级碳结构作为存储器件的基础。单壁碳纳米管将包含一个带电的巴基球。那个巴基球会紧紧地粘在管子的一端或另一端。我们根据球在管子的哪一边来分配设备的位值。其结果是一个高速的、非易失性的内存位。我们为这些设备的互连提出了一些方案,并检查了一些已知的电气问题。
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引用次数: 8
Built in self test for ring addressed FIFOs with transparent latches 内置自检环寻址fifo与透明锁存器
L. Fenstermaker, Ilyoung Kim, J. Lewandowski, J. J. Nagy
The use of special purpose complex embedded memories is becoming increasingly common. Their complex functionality, large sizes, decreasing feature sizes, and limited controllability/observability combine to make testing ever more difficult. In this paper, we describe a built in self test (BIST) method for testing ring addressed first in first out memories (FIFOs) that use transparent input latches for applications that require high data rates. The method used is compared to previous results for ring addressed FIFOs with edge triggered input latches. Several different special test modes are used to provide both more efficient and more complete BIST.
特殊用途复杂嵌入式存储器的使用正变得越来越普遍。它们复杂的功能、巨大的尺寸、不断减少的特性尺寸以及有限的可控性/可观察性使得测试变得更加困难。在本文中,我们描述了一种用于测试环寻址先入先出存储器(fifo)的内置自检(BIST)方法,该方法使用透明输入锁存器用于需要高数据速率的应用。所使用的方法是比较以前的结果环寻址fifo与边缘触发输入锁存器。使用几种不同的特殊测试模式来提供更高效和更完整的BIST。
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引用次数: 0
Computing in memory architectures for digital image processing 用于数字图像处理的存储器结构计算
L. Roth, L. D. Coraor, D. Landis, P. T. Hulina, S. Deno
Continuing improvements in semiconductor fabrication density are enabling new classes of system-on-a-chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these new architectures can be custom tailored to the demands of real-time digital image processing. This paper evaluates several candidate designs, using the criteria of image processing performance, flexibility, manufacturability, and fabrication cost.
半导体制造密度的持续改进使结合了广泛处理逻辑和高密度存储器的新型片上系统架构成为可能。这些新架构的许多功能可以根据实时数字图像处理的需求进行定制。本文以图像处理性能、灵活性、可制造性和制造成本为标准,对几种候选设计进行了评估。
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引用次数: 5
Modeling and testing transistor faults in content-addressable memories 内容可寻址存储器中晶体管故障的建模和测试
P. R. Sidorowicz
A behavioral analysis of transistor faults and cell-stuck-at faults in a n-word by l-bit static CMOS CAM array is presented. First, a CAM cell is analyzed at the transistor-network, event-sequence and finite-state machine level. Then, a transistor stuck-(on/open) and cell-stuck-at fault model for a CAM is defined. We show that two out of eighteen possible CAM cell's transistor faults cannot be tested reliably by functional tests; however among faults that are testable, are all those which comprise data-retention faults. We also show that a test, originally designed to detect input stuck-at faults, also detects all reliably testable transistor faults and all cell-stuck-at faults in the model.
提出了一种基于l位静态CMOS CAM阵列的n字晶体管故障和卡芯故障的行为分析方法。首先,在晶体管网络、事件序列和有限状态机层面对CAM单元进行了分析。然后,定义了CAM的晶体管卡(开/开)和电池卡(开/开)故障模型。我们表明,18个可能的CAM电池的晶体管故障中有两个不能通过功能测试可靠地测试出来;然而,在可测试的错误中,所有包含数据保留错误的错误都是可测试的。我们还表明,最初设计用于检测输入卡死故障的测试也可以检测模型中所有可可靠测试的晶体管故障和所有电池卡死故障。
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引用次数: 6
A fast test to generate flash memory threshold voltage distribution map 快速测试生成闪存阈值电压分布图
Raju Khubchandani
This paper describes a method to determine threshold voltage (V/sub th/) distribution as a multi-colored bitmap of the die. That is, a visual indication of relative threshold voltages on different areas of the die is provided. The spatial distribution of threshold voltage is felt to be more informative than conventional techniques which provide results as a bell-curve Gauss distribution plot of threshold voltage versus number of cells. The time required for test execution (including data gathering) is considerably less than the time taken by conventional methods.
本文描述了一种以多色位图的方式确定阈值电压(V/sub /)分布的方法。也就是说,提供了在模具不同区域上的相对阈值电压的视觉指示。阈值电压的空间分布被认为比传统技术提供的阈值电压随细胞数的钟形曲线高斯分布图更有信息量。测试执行所需的时间(包括数据收集)比传统方法所花费的时间要少得多。
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引用次数: 3
Determining redundancy requirements for memory arrays with critical area analysis 通过关键区域分析确定存储器阵列的冗余要求
J. Segal, S. Bakarian, J. E. Colburn, Madan Kumar, Chang Hong, A. Shubat
Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations.
利用内联缺陷数据、单元布局的关键区域分析以及将关键区域与电气故障关联的基于规则的算法,我们可以确定任何存储电路的最佳冗余配置。该技术预测了一系列冗余配置的产量,并根据产量和模具尺寸的考虑,找到任何存储器设计的最佳冗余行和列数。
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引用次数: 20
Tutorial: characterizing SDRAMs 教程:表征dram
J. Voilrath
This paper presents characterization methods for an SDRAM in a manufacturing environment. Contact tests, dc tests, basic functional tests, signal margin tests and retention characterization are shown. Measurement of the cell signal is used as an example for pico probing. Special test modes for SDRAMs which can be used to aid characterization and failure analysis (FA) are discussed.
本文介绍了在制造环境下SDRAM的表征方法。显示了接触测试、直流测试、基本功能测试、信号裕度测试和保持特性。以微探针为例,对蜂窝信号进行测量。讨论了可用于辅助表征和失效分析(FA)的sdram特殊测试模式。
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引用次数: 3
The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval 动态关联存取存储器芯片及其在SIMD处理和全文数据库检索中的应用
G. Lipovski, Clement T. Yu
Dynamic Associative Access Memory (DAAM) chips are processor-in-memory chips wherein a large number of small processing elements are put in a DRAM's sense amps. Thousands of these chips will be mounted on "memory boards" in "TONY" full-text database servers. This paper shows that multibank memory eliminates DRAM latency, and a one-bit ALU that can be made into an associative processor, with the addition of one gate. This paper shows how this unconventional technology offers nearly three orders of magnitude better cost performance than a Pentium microprocessor, nearly 1,000 MIPs per dollar of chip cost for the DAAM compared to about 1 MIPs per dollar of chip cost for the Pentium. This paper shows that a TONY server system using this chip will handle over a million on-line users, more than two orders of magnitude more cost-effective than the best current database machines, and a TONY server stores a page of text for approximately five cents (the cost of duplicating the printed page).
动态关联存取存储器(DAAM)芯片是一种内存处理器芯片,其中大量的小处理元件被放入DRAM的感测放大器中。数千个这样的芯片将被安装在“TONY”全文数据库服务器的“内存板”上。本文证明了多组存储器消除了DRAM的延迟,并且通过增加一个门,可以将一个1位ALU制成一个关联处理器。本文展示了这种非常规技术如何提供比Pentium微处理器高近三个数量级的性价比,DAAM每美元芯片成本近1,000 MIPs,而Pentium每美元芯片成本约为1 MIPs。本文表明,使用这种芯片的TONY服务器系统将处理超过一百万在线用户,比当前最好的数据库机器的成本效益高出两个数量级以上,并且TONY服务器存储一页文本的成本约为5美分(复制打印页面的成本)。
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引用次数: 20
期刊
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing
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