Design validation of .18 /spl mu/m 1 GHz cache and register arrays

Abstract

This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7LM copper BEOL technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be discussed. Aggressive product cycle time SRAM applications for IBM's S/390 L2 cache chips require multifaceted approaches to address the following: (i) SRAM operability in product-like clocking and ABIST environments. (ii) Demonstration of yield using 2-dimensional redundancy. (iii) Characterization of SRAM signals used in the macro timing rules. (iv) Obtain high volume pre-product manufacturing test experience. (v) Verify SRAM functionality at technology stress test conditions. Prototype test chips in IBM's .18 /spl mu/m technology have provided opportunities to investigate these areas, greatly mitigate risks associated with ever decreasing product design cycles and exercise the SRAM timing rules and logic models in a product-like application.