A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS AND ITS ERROR DETECTION CAPABILITY

Abstract

New principles for the on-line system-level test of multiprocessors are proposed, based on signaturing and monitoring data dependences together with control dependences. I n order to help in this process, each data routing message contains both source and destination addresses. At each message source, the destination addresses of the outgoing messages are compressed. At the same time, at each destination, the source addresses of all incoming messages are compressed. Concurrent compression of the instructions executed by the PES is also possible. The resulting signatures are compared at the end of each computational block with reference signatures created at compilation time. An analytical model and an analysis for the address compression process used for the monitoring the data routing process are provided. The aliasing probability for the error detection process is studied, obtaining closedform expressions in the single error case and upper bounds in the multiple error case.