R. Huang, P. W. Liu, E. C. Liu, W. Chiang, S. Tsai, J. Tsai, T. Shen, C. Tsai, C. Tsai, G. H. Ma
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引用次数: 0
Abstract
In this paper, we have systematically investigated the factors for performance enhancement on sub-32nm CMOS technology. We report that PMOS gains the drive current by slim spacer, S/D silicide resistance reduction by e-SiGe, and compressive CESL. The three factors improve the PMOS performance by 7%, 10% and 25% respectively. Combined with the three factors can gain the device drive current 30%. In addition, the optimized integration scheme can reduce NMOS extension resistance. The main cause is that post e-SiGe clean processes would loss the extension dopant and increases the extension resistance. We successfully reduce the NMOS total resistance 22% compared to control without compromise PMOS device performance.
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