Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159336
T. Hsu, H. Lue, S. Lai, Y. King, K. Hsieh, Rich Liu, Chih-Yuan Lu
The reliability of sub-40nm SONOS NAND devices with various tunnel oxide thickness and FinFET structures are studied for future NAND Flash application. SONOS intrinsically has slow erase speed and high erase saturation for tunnel oxide ranging from 25 to 45 Å. Furthermore, the endurance degradation occurs very early at low P/E≪10, owing to the nature of electron de-trapping mechanism at tunnel oxide ≫ 20A. Thus planar SONOS is not suitable for NAND Flash applications. On the other hand, when SONOS is applied to FinFET structure, significantly faster erase speed is obtained, owing to the field enhancement effect. However, it is still hard to erase below the initial Vt. We conclude that barrier engineering, such as BE-SONOS is more efficient in providing faster erase speed at lower erase voltages without endurance degradation. We also estimated the large density (4Mb) array distribution of sub-40 nm SONOS and BE-SONOS devices, and found that the distribution width is quite insensitive to the tunnel oxide thickness. This suggests that for future scaled NAND devices the edge effect is more important in determining the P/E distribution than the tunnel oxide thickness variation.
{"title":"Reliability of planar and FinFET SONOS devices for NAND flash applications - Field enhancement vs. barrier engineering","authors":"T. Hsu, H. Lue, S. Lai, Y. King, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/VTSA.2009.5159336","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159336","url":null,"abstract":"The reliability of sub-40nm SONOS NAND devices with various tunnel oxide thickness and FinFET structures are studied for future NAND Flash application. SONOS intrinsically has slow erase speed and high erase saturation for tunnel oxide ranging from 25 to 45 Å. Furthermore, the endurance degradation occurs very early at low P/E≪10, owing to the nature of electron de-trapping mechanism at tunnel oxide ≫ 20A. Thus planar SONOS is not suitable for NAND Flash applications. On the other hand, when SONOS is applied to FinFET structure, significantly faster erase speed is obtained, owing to the field enhancement effect. However, it is still hard to erase below the initial Vt. We conclude that barrier engineering, such as BE-SONOS is more efficient in providing faster erase speed at lower erase voltages without endurance degradation. We also estimated the large density (4Mb) array distribution of sub-40 nm SONOS and BE-SONOS devices, and found that the distribution width is quite insensitive to the tunnel oxide thickness. This suggests that for future scaled NAND devices the edge effect is more important in determining the P/E distribution than the tunnel oxide thickness variation.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123045952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159277
M. Liao, L. Yeh, J. C. Lu, M. H. Yu, L. T. Wang, J. Wu, P. Jeng, T. Lee, S. Jang
Strained-Si technology is the Holy Grail for present semiconductor industry and is used extensively to boost the device performance, recently. However, the limitation of strained-Si technology has greatly perplexed us and need to investigate in detail. In this work, the low temperature ballistic measurement enables us to discriminate the origin of mobility enhancement under stress from the reduction of effective mass and/or the influence of different scattering mechanisms. It is found that the electron mobility enhancement under stress will become less sensitive when the gate length of device reaches ∼100 nm. The real mechanism of this phenomenon have be proved to the characteristic of device ballistic transport and the optimal stress design developed in this work can further extend the limitation of Strained-Si technology to the smaller gate length region (technology node) (Fig. 1).
{"title":"An investigation about the limitation of strained-Si technology","authors":"M. Liao, L. Yeh, J. C. Lu, M. H. Yu, L. T. Wang, J. Wu, P. Jeng, T. Lee, S. Jang","doi":"10.1109/VTSA.2009.5159277","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159277","url":null,"abstract":"Strained-Si technology is the Holy Grail for present semiconductor industry and is used extensively to boost the device performance, recently. However, the limitation of strained-Si technology has greatly perplexed us and need to investigate in detail. In this work, the low temperature ballistic measurement enables us to discriminate the origin of mobility enhancement under stress from the reduction of effective mass and/or the influence of different scattering mechanisms. It is found that the electron mobility enhancement under stress will become less sensitive when the gate length of device reaches ∼100 nm. The real mechanism of this phenomenon have be proved to the characteristic of device ballistic transport and the optimal stress design developed in this work can further extend the limitation of Strained-Si technology to the smaller gate length region (technology node) (Fig. 1).","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122455478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159288
T. Bao, H. Chen, C.J. Lee, H. Lu, S. Shue, C. Yu
Various integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.
{"title":"Low capacitance approaches for 22nm generation Cu interconnect","authors":"T. Bao, H. Chen, C.J. Lee, H. Lu, S. Shue, C. Yu","doi":"10.1109/VTSA.2009.5159288","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159288","url":null,"abstract":"Various integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128585459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159305
D. Park, K. Stein, K. Schruefer, Y. Lee, J. Han, W. Li, H. Yin, C. Pacha, N. Kim, M. Ostermayr, M. Eller, S. Kim, K. Kim, S. Han, K. von Arnim, N. Moumen, M. Hatzistergos, T. Tang, R. Loesing, X. Chen, D. Jaeger, H. Zhuang, J. Chen, W. Yan, T. Kanarsky, M. Chowdhury, J. Haetty, D. Schepis, M. Chudzik, V.-Y. Theon, S. Samavedam, V. Narayanan, M. Sherony, R. Lindsay, A. Steegen, R. Divakaruni, M. Khare
This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.
{"title":"High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond","authors":"D. Park, K. Stein, K. Schruefer, Y. Lee, J. Han, W. Li, H. Yin, C. Pacha, N. Kim, M. Ostermayr, M. Eller, S. Kim, K. Kim, S. Han, K. von Arnim, N. Moumen, M. Hatzistergos, T. Tang, R. Loesing, X. Chen, D. Jaeger, H. Zhuang, J. Chen, W. Yan, T. Kanarsky, M. Chowdhury, J. Haetty, D. Schepis, M. Chudzik, V.-Y. Theon, S. Samavedam, V. Narayanan, M. Sherony, R. Lindsay, A. Steegen, R. Divakaruni, M. Khare","doi":"10.1109/VTSA.2009.5159305","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159305","url":null,"abstract":"This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116498450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159270
H. Aoki, T. Masuzumi, M. Hara, D. Watanabe, C. Kimura, T. Sugino
We have investigated the properties of boron carbon nitride containing hydrogen (BCNH) film deposited by using tris (dimethylamino)boron (TMAB) gas. The dielectric constant (k) of the BCNH film was achieved as low as 1.8 by deposition with a low RP power (10W). The film has a sufficient Young's modulus as high as 26 GPa. In addition, k-value of BCNH film is more stable compared with conventional BCN film.
{"title":"Boron carbon nitride film containing hydrogen for 2nm node low-k interconnection","authors":"H. Aoki, T. Masuzumi, M. Hara, D. Watanabe, C. Kimura, T. Sugino","doi":"10.1109/VTSA.2009.5159270","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159270","url":null,"abstract":"We have investigated the properties of boron carbon nitride containing hydrogen (BCNH) film deposited by using tris (dimethylamino)boron (TMAB) gas. The dielectric constant (k) of the BCNH film was achieved as low as 1.8 by deposition with a low RP power (10W). The film has a sufficient Young's modulus as high as 26 GPa. In addition, k-value of BCNH film is more stable compared with conventional BCN film.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132309984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159294
H. Hsu, Chun‐Hu Cheng, B. Tsui
Hafnium titanate (HfTiO) film was adapted as the insulator of MIM capacitors for RF/Analog ICs applications. Low leakage current of 3.4×10−8 A/cm2 at −1V and high capacitance density of 17.5fF/µm2 were obtained. A N2-plasma treatment on HfTiO films can further reduce leakage current by two orders of magnitude and no apparent degradation is observed on the capacitance density and voltage coefficient of capacitance (VCC) properties. Capacitance density of 5.1fF/µm2, leakage current of 1.3×10−9A/cm2, and parabolic VCC value of 40ppm/V2 can be achieved by 51nm thick HfTiO film. These results meet the RF/analog requirements in 2012 predicted by ITRS.
{"title":"High performance metal/insulator/metal capacitors using HfTiO as dielectric","authors":"H. Hsu, Chun‐Hu Cheng, B. Tsui","doi":"10.1109/VTSA.2009.5159294","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159294","url":null,"abstract":"Hafnium titanate (HfTiO) film was adapted as the insulator of MIM capacitors for RF/Analog ICs applications. Low leakage current of 3.4×10<sup>−8</sup> A/cm<sup>2</sup> at −1V and high capacitance density of 17.5fF/µm<sup>2</sup> were obtained. A N<inf>2</inf>-plasma treatment on HfTiO films can further reduce leakage current by two orders of magnitude and no apparent degradation is observed on the capacitance density and voltage coefficient of capacitance (VCC) properties. Capacitance density of 5.1fF/µm<sup>2</sup>, leakage current of 1.3×10<sup>−9</sup>A/cm<sup>2</sup>, and parabolic VCC value of 40ppm/V<sup>2</sup> can be achieved by 51nm thick HfTiO film. These results meet the RF/analog requirements in 2012 predicted by ITRS.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127052722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159291
J. Price, G. Bersuker, P. Lysaght, H. Tseng
This paper presents a new method utilizing spectroscopic ellipsometry (SE) to non-invasively identify the oxygen vacancy defects located in the bottom interfacial SiO2 layer (BIF) of the scaled high-k/ metal gate stacks. Discrete absorption features within the bandgap of the SiO2 BIF are identified, and their relation to both intrinsic and process-induced defects is proposed. Sensitivity to changes in these defects with different process conditions is demonstrated, along with evidence suggesting that these same defects may contribute to the mechanism associated with the Vfb roll-off phenomenon.
{"title":"Extending spectroscopic ellipsometry for identification of electrically active defects in Si/SiO2/high-k/metal gate stacks","authors":"J. Price, G. Bersuker, P. Lysaght, H. Tseng","doi":"10.1109/VTSA.2009.5159291","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159291","url":null,"abstract":"This paper presents a new method utilizing spectroscopic ellipsometry (SE) to non-invasively identify the oxygen vacancy defects located in the bottom interfacial SiO2 layer (BIF) of the scaled high-k/ metal gate stacks. Discrete absorption features within the bandgap of the SiO2 BIF are identified, and their relation to both intrinsic and process-induced defects is proposed. Sensitivity to changes in these defects with different process conditions is demonstrated, along with evidence suggesting that these same defects may contribute to the mechanism associated with the Vfb roll-off phenomenon.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126457149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159278
B. Rajendran, M. Breitwisch, R. Cheek, M. Lee, Y. Shih, H. Lung, C. Lam
We demonstrate poly-Silicon emitter vertical PNP Bipolar Junction Transistors (BJTs) that could be used as access devices for Phase Change Memory. The device arrays fabricated using a 180nm BiCMOS process exhibit current drive capability in excess of 10mA/µm2, On-Off ratio greater than six orders of magnitude and excellent cross-talk immunity. Our process integration scheme could be extended to enable a high-density Phase Change Memory technology.
{"title":"Characterization of poly-Silicon emitter BJTs as access devices for Phase Change Memory","authors":"B. Rajendran, M. Breitwisch, R. Cheek, M. Lee, Y. Shih, H. Lung, C. Lam","doi":"10.1109/VTSA.2009.5159278","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159278","url":null,"abstract":"We demonstrate poly-Silicon emitter vertical PNP Bipolar Junction Transistors (BJTs) that could be used as access devices for Phase Change Memory. The device arrays fabricated using a 180nm BiCMOS process exhibit current drive capability in excess of 10mA/µm2, On-Off ratio greater than six orders of magnitude and excellent cross-talk immunity. Our process integration scheme could be extended to enable a high-density Phase Change Memory technology.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121123864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159275
P. W. Liu, T. Kuo, C. I. Li, Y. R. Wang, R. Huang, C. Tsai, C. T. Tsai, G. H. Ma
The dopant and thermal interaction on solid phase epitaxy (SPE) formed SiC has been investigated. We have studied the impact on substitutional carbon concentration ([C]sub) from various thermal steps including low temperature anneal, SiGe epitaxy thermal budget, RTP, and laser anneal (LSA). Regarding the integration scheme for implementing embedded SiC (eSiC) S/D on NMOS performance enhancement, both post-LDD and post-S/D schemes were studied. The higher [C]sub in post-LDD scheme was observed and the S/D dopants were found to enhance the carbon precipitation into interstitial with conventional RTP/LSA activation thermal processes. The phosphorous implant is also found to degrade [C]sub in comparison to As implant. The higher [C]sub and proximity to channel of formed eSiC in post-LDD scheme are beneficial to device performance. The fabricated eSiC S/D NMOS shows 31% mobility improvement and 7% current enhancement.
{"title":"Dopant and thermal interaction on SPE formed SiC for NMOS performance enhancement","authors":"P. W. Liu, T. Kuo, C. I. Li, Y. R. Wang, R. Huang, C. Tsai, C. T. Tsai, G. H. Ma","doi":"10.1109/VTSA.2009.5159275","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159275","url":null,"abstract":"The dopant and thermal interaction on solid phase epitaxy (SPE) formed SiC has been investigated. We have studied the impact on substitutional carbon concentration ([C]sub) from various thermal steps including low temperature anneal, SiGe epitaxy thermal budget, RTP, and laser anneal (LSA). Regarding the integration scheme for implementing embedded SiC (eSiC) S/D on NMOS performance enhancement, both post-LDD and post-S/D schemes were studied. The higher [C]sub in post-LDD scheme was observed and the S/D dopants were found to enhance the carbon precipitation into interstitial with conventional RTP/LSA activation thermal processes. The phosphorous implant is also found to degrade [C]sub in comparison to As implant. The higher [C]sub and proximity to channel of formed eSiC in post-LDD scheme are beneficial to device performance. The fabricated eSiC S/D NMOS shows 31% mobility improvement and 7% current enhancement.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115320211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159308
Jack J. H. Chen, S.J. Lin, T. Fang, S. Chang, F. Krečinić, B. Lin
Based on the maturing MEMS capabilities and electronics technologies, the cost effective high-throughput MEBML2, at ≫100 WPH and footprint similar to an optical scanner, can be realized. Resolution, proximity correction, wafer heating and data rate shall not be problems for 5 keV at such high throughput. Another big advantage of focusing on MEBML2 as the lithography solution for 32-nm HP node and beyond is that it only needs investments on developing this tool. Unlike EUV and double patterning, which need enormous investments on the mask infrastructure and process development, besides just the cost of the lithography tool. However, the success of the MEBML2 technology still requires enormous industrial support and investments, which may happen only when it is commonly viewed as one of the mainstream technologies for high-volume manufacturing. To catch up manufacturing of the 32-nm HP node, the clustered platform has to be ready by 2012, which needs big platform suppliers' involvement very soon.
{"title":"Multiple electron beam maskless lithography for high-volume manufacturing","authors":"Jack J. H. Chen, S.J. Lin, T. Fang, S. Chang, F. Krečinić, B. Lin","doi":"10.1109/VTSA.2009.5159308","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159308","url":null,"abstract":"Based on the maturing MEMS capabilities and electronics technologies, the cost effective high-throughput MEBML2, at ≫100 WPH and footprint similar to an optical scanner, can be realized. Resolution, proximity correction, wafer heating and data rate shall not be problems for 5 keV at such high throughput. Another big advantage of focusing on MEBML2 as the lithography solution for 32-nm HP node and beyond is that it only needs investments on developing this tool. Unlike EUV and double patterning, which need enormous investments on the mask infrastructure and process development, besides just the cost of the lithography tool. However, the success of the MEBML2 technology still requires enormous industrial support and investments, which may happen only when it is commonly viewed as one of the mainstream technologies for high-volume manufacturing. To catch up manufacturing of the 32-nm HP node, the clustered platform has to be ready by 2012, which needs big platform suppliers' involvement very soon.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131539338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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