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2009 International Symposium on VLSI Technology, Systems, and Applications最新文献

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Reliability of planar and FinFET SONOS devices for NAND flash applications - Field enhancement vs. barrier engineering 用于NAND闪存应用的平面和FinFET SONOS器件的可靠性-场增强与屏障工程
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159336
T. Hsu, H. Lue, S. Lai, Y. King, K. Hsieh, Rich Liu, Chih-Yuan Lu
The reliability of sub-40nm SONOS NAND devices with various tunnel oxide thickness and FinFET structures are studied for future NAND Flash application. SONOS intrinsically has slow erase speed and high erase saturation for tunnel oxide ranging from 25 to 45 Å. Furthermore, the endurance degradation occurs very early at low P/E≪10, owing to the nature of electron de-trapping mechanism at tunnel oxide ≫ 20A. Thus planar SONOS is not suitable for NAND Flash applications. On the other hand, when SONOS is applied to FinFET structure, significantly faster erase speed is obtained, owing to the field enhancement effect. However, it is still hard to erase below the initial Vt. We conclude that barrier engineering, such as BE-SONOS is more efficient in providing faster erase speed at lower erase voltages without endurance degradation. We also estimated the large density (4Mb) array distribution of sub-40 nm SONOS and BE-SONOS devices, and found that the distribution width is quite insensitive to the tunnel oxide thickness. This suggests that for future scaled NAND devices the edge effect is more important in determining the P/E distribution than the tunnel oxide thickness variation.
研究了不同隧道氧化物厚度和FinFET结构的亚40nm SONOS NAND器件的可靠性,为未来NAND闪存的应用奠定了基础。SONOS本质上具有较慢的擦除速度和高擦除饱和度,隧道氧化物范围为25至45 Å。此外,在低P/E < 10时,由于隧道氧化物在< 20A >处的电子脱陷机制,耐久性下降发生得非常早。因此,平面SONOS不适合NAND闪存应用。另一方面,当SONOS应用于FinFET结构时,由于场增强效应,可以获得明显更快的擦除速度。然而,在初始电压下仍然很难擦除。我们得出结论,屏障工程,如BE-SONOS,在较低擦除电压下提供更快的擦除速度而不会降低耐用性。我们还估计了sub-40 nm SONOS和BE-SONOS器件的大密度(4Mb)阵列分布,发现分布宽度对隧道氧化物厚度非常不敏感。这表明,对于未来的缩放NAND器件,边缘效应在决定P/E分布方面比隧道氧化物厚度变化更重要。
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引用次数: 9
An investigation about the limitation of strained-Si technology 应变硅技术的局限性研究
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159277
M. Liao, L. Yeh, J. C. Lu, M. H. Yu, L. T. Wang, J. Wu, P. Jeng, T. Lee, S. Jang
Strained-Si technology is the Holy Grail for present semiconductor industry and is used extensively to boost the device performance, recently. However, the limitation of strained-Si technology has greatly perplexed us and need to investigate in detail. In this work, the low temperature ballistic measurement enables us to discriminate the origin of mobility enhancement under stress from the reduction of effective mass and/or the influence of different scattering mechanisms. It is found that the electron mobility enhancement under stress will become less sensitive when the gate length of device reaches ∼100 nm. The real mechanism of this phenomenon have be proved to the characteristic of device ballistic transport and the optimal stress design developed in this work can further extend the limitation of Strained-Si technology to the smaller gate length region (technology node) (Fig. 1).
应变硅技术是当前半导体工业的圣杯,近年来被广泛用于提高器件性能。然而,应变硅技术的局限性一直困扰着我们,需要深入研究。在这项工作中,低温弹道测量使我们能够从有效质量的减少和/或不同散射机制的影响中区分应力下迁移率增强的来源。发现当器件栅长达到~ 100 nm时,应力下电子迁移率的增强变得不那么敏感。这一现象的真实机理已被证明是器件弹道输运的特征,本工作所开发的最优应力设计可以进一步将应变硅技术的限制扩展到更小的栅长区域(技术节点)(图1)。
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引用次数: 1
Low capacitance approaches for 22nm generation Cu interconnect 22nm代铜互连的低电容方法
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159288
T. Bao, H. Chen, C.J. Lee, H. Lu, S. Shue, C. Yu
Various integration approaches, including homogeneous porous Low-k and air gaps, for low-capacitance solution were investigated for 22nm Cu interconnect technology and beyond. For homogeneous Low-k approach, K=2.0 Low-k material is successfully integrated with Cu. Up to 15% line to line capacitance reduction compared with LK-1 (K= 2.5) was demonstrated by a damage-less etching and CMP process. For air gap approach, a cost-effective and Selective air gaps formation process was developed. Air gaps are selectively formed only at narrow spacing between conduction lines without additional processes.
研究了22nm铜互连技术及以后的低电容解决方案的各种集成方法,包括均匀多孔Low-k和气隙。对于均匀Low-k方法,K=2.0 Low-k材料与Cu成功集成。与LK-1 (K= 2.5)相比,通过无损伤蚀刻和CMP工艺证明了高达15%的线对线电容降低。对于气隙方法,开发了一种具有成本效益和选择性的气隙形成工艺。气隙仅在导线之间的窄间距处选择性形成,无需额外的工艺。
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引用次数: 5
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond 高κ/金属栅极低功耗批量技术-标准CMOS逻辑电路,微处理器关键路径副本和45纳米及以上SRAM的性能评估
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159305
D. Park, K. Stein, K. Schruefer, Y. Lee, J. Han, W. Li, H. Yin, C. Pacha, N. Kim, M. Ostermayr, M. Eller, S. Kim, K. Kim, S. Han, K. von Arnim, N. Moumen, M. Hatzistergos, T. Tang, R. Loesing, X. Chen, D. Jaeger, H. Zhuang, J. Chen, W. Yan, T. Kanarsky, M. Chowdhury, J. Haetty, D. Schepis, M. Chudzik, V.-Y. Theon, S. Samavedam, V. Narayanan, M. Sherony, R. Lindsay, A. Steegen, R. Divakaruni, M. Khare
This paper presents performance evaluation of high-κ/metal gate (HK/MG) process on an industry standard 45nm low power microprocessor built on bulk substrate. CMOS devices built with HK/MG demonstrate 50% improvement in NFET and 65% improvement in PFET drive current when compared with industry standard 45nm Poly/SiON devices. No additional stress elements were used for this performance gain. The critical path circuits of this low power microprocessor built with HK/MG show dynamic performance gain over 50% at same supply voltage and 36% lower dynamic energy at same performance. Superior SRAM minimum operating voltage characteristics are achieved due to Vt variability reduction from HK/MG. Analog circuit functionality is demonstrated by a fully integrated PLL circuitry without any modification to process.
本文介绍了高κ/金属栅极(HK/MG)工艺在工业标准45nm低功耗微处理器上的性能评价。与工业标准的45纳米Poly/SiON器件相比,用HK/MG制造的CMOS器件的fet提高了50%,fet驱动电流提高了65%。为了提高性能,没有使用额外的应力元件。采用HK/MG构建的低功耗微处理器关键路径电路在相同电源电压下动态性能提高50%以上,在相同性能下动态能量降低36%。优越的SRAM最小工作电压特性,由于Vt变异性从HK/MG降低实现。模拟电路的功能由一个完全集成的锁相环电路来演示,而不需要对过程进行任何修改。
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引用次数: 0
Boron carbon nitride film containing hydrogen for 2nm node low-k interconnection 含氢硼碳氮化膜用于2nm节点低k互连
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159270
H. Aoki, T. Masuzumi, M. Hara, D. Watanabe, C. Kimura, T. Sugino
We have investigated the properties of boron carbon nitride containing hydrogen (BCNH) film deposited by using tris (dimethylamino)boron (TMAB) gas. The dielectric constant (k) of the BCNH film was achieved as low as 1.8 by deposition with a low RP power (10W). The film has a sufficient Young's modulus as high as 26 GPa. In addition, k-value of BCNH film is more stable compared with conventional BCN film.
研究了三(二甲氨基)硼(TMAB)气沉积含氢硼碳氮(BCNH)薄膜的性能。在低RP功率(10W)下沉积,BCNH薄膜的介电常数(k)低至1.8。该薄膜具有足够的杨氏模量高达26 GPa。此外,BCNH膜的k值比常规BCN膜更稳定。
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引用次数: 2
High performance metal/insulator/metal capacitors using HfTiO as dielectric 高性能金属/绝缘体/金属电容器采用HfTiO作为电介质
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159294
H. Hsu, Chun‐Hu Cheng, B. Tsui
Hafnium titanate (HfTiO) film was adapted as the insulator of MIM capacitors for RF/Analog ICs applications. Low leakage current of 3.4×10−8 A/cm2 at −1V and high capacitance density of 17.5fF/µm2 were obtained. A N2-plasma treatment on HfTiO films can further reduce leakage current by two orders of magnitude and no apparent degradation is observed on the capacitance density and voltage coefficient of capacitance (VCC) properties. Capacitance density of 5.1fF/µm2, leakage current of 1.3×10−9A/cm2, and parabolic VCC value of 40ppm/V2 can be achieved by 51nm thick HfTiO film. These results meet the RF/analog requirements in 2012 predicted by ITRS.
采用钛酸铪(HfTiO)薄膜作为射频/模拟集成电路中MIM电容器的绝缘体。在−1V时,获得了3.4×10−8 A/cm2的低漏电流和17.5fF/µm2的高电容密度。氮气等离子体处理可使泄漏电流进一步降低两个数量级,而电容密度和电容电压系数(VCC)性能没有明显下降。采用51nm厚的HfTiO薄膜,电容密度为5.1fF/µm2,漏电流为1.3×10−9A/cm2,抛物VCC值为40ppm/V2。这些结果满足了ITRS预测的2012年射频/模拟需求。
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引用次数: 4
Extending spectroscopic ellipsometry for identification of electrically active defects in Si/SiO2/high-k/metal gate stacks 扩展椭圆偏振光谱法识别Si/SiO2/高k/金属栅堆中的电活性缺陷
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159291
J. Price, G. Bersuker, P. Lysaght, H. Tseng
This paper presents a new method utilizing spectroscopic ellipsometry (SE) to non-invasively identify the oxygen vacancy defects located in the bottom interfacial SiO2 layer (BIF) of the scaled high-k/ metal gate stacks. Discrete absorption features within the bandgap of the SiO2 BIF are identified, and their relation to both intrinsic and process-induced defects is proposed. Sensitivity to changes in these defects with different process conditions is demonstrated, along with evidence suggesting that these same defects may contribute to the mechanism associated with the Vfb roll-off phenomenon.
本文提出了一种利用椭圆偏振光谱(SE)非侵入性识别高k/金属栅极堆底部界面SiO2层(BIF)氧空位缺陷的新方法。研究了二氧化硅BIF带隙内的离散吸收特征,并提出了其与本征缺陷和工艺缺陷的关系。在不同的工艺条件下,对这些缺陷变化的敏感性被证明,同时有证据表明,这些相同的缺陷可能有助于与Vfb滚脱现象相关的机制。
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引用次数: 4
Characterization of poly-Silicon emitter BJTs as access devices for Phase Change Memory 多晶硅发射极bjt作为相变存储器接入器件的特性研究
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159278
B. Rajendran, M. Breitwisch, R. Cheek, M. Lee, Y. Shih, H. Lung, C. Lam
We demonstrate poly-Silicon emitter vertical PNP Bipolar Junction Transistors (BJTs) that could be used as access devices for Phase Change Memory. The device arrays fabricated using a 180nm BiCMOS process exhibit current drive capability in excess of 10mA/µm2, On-Off ratio greater than six orders of magnitude and excellent cross-talk immunity. Our process integration scheme could be extended to enable a high-density Phase Change Memory technology.
我们展示了可以用作相变存储器访问器件的多晶硅发射极垂直PNP双极结晶体管(BJTs)。采用180nm BiCMOS工艺制造的器件阵列具有超过10mA/µm2的电流驱动能力、大于6个数量级的通断比和出色的串扰抗扰性。我们的工艺集成方案可以扩展到实现高密度相变存储器技术。
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引用次数: 6
Dopant and thermal interaction on SPE formed SiC for NMOS performance enhancement 掺杂剂和热相互作用对固相萃取形成的碳化硅性能的增强
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159275
P. W. Liu, T. Kuo, C. I. Li, Y. R. Wang, R. Huang, C. Tsai, C. T. Tsai, G. H. Ma
The dopant and thermal interaction on solid phase epitaxy (SPE) formed SiC has been investigated. We have studied the impact on substitutional carbon concentration ([C]sub) from various thermal steps including low temperature anneal, SiGe epitaxy thermal budget, RTP, and laser anneal (LSA). Regarding the integration scheme for implementing embedded SiC (eSiC) S/D on NMOS performance enhancement, both post-LDD and post-S/D schemes were studied. The higher [C]sub in post-LDD scheme was observed and the S/D dopants were found to enhance the carbon precipitation into interstitial with conventional RTP/LSA activation thermal processes. The phosphorous implant is also found to degrade [C]sub in comparison to As implant. The higher [C]sub and proximity to channel of formed eSiC in post-LDD scheme are beneficial to device performance. The fabricated eSiC S/D NMOS shows 31% mobility improvement and 7% current enhancement.
研究了固相外延(SPE)制备碳化硅过程中掺杂剂和热相互作用。我们研究了低温退火、SiGe外延热收支、RTP和激光退火(LSA)等不同热步骤对取代碳浓度([C]sub)的影响。针对提高NMOS性能的嵌入式SiC (eSiC) S/D集成方案,研究了后ldd方案和后S/D方案。在后ldd方案中观察到较高的[C]sub,并且发现S/D掺杂剂可以通过传统的RTP/LSA激活热过程增强碳向间隙的沉淀。与砷植入物相比,磷植入物也被发现可降解[C]亚。在后ldd方案中,较高的[C]sub和接近通道的形成eSiC有利于器件性能。制备的eSiC S/D NMOS迁移率提高31%,电流增强7%。
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引用次数: 0
Multiple electron beam maskless lithography for high-volume manufacturing 用于大批量生产的多电子束无掩模光刻技术
Pub Date : 2009-04-27 DOI: 10.1109/VTSA.2009.5159308
Jack J. H. Chen, S.J. Lin, T. Fang, S. Chang, F. Krečinić, B. Lin
Based on the maturing MEMS capabilities and electronics technologies, the cost effective high-throughput MEBML2, at ≫100 WPH and footprint similar to an optical scanner, can be realized. Resolution, proximity correction, wafer heating and data rate shall not be problems for 5 keV at such high throughput. Another big advantage of focusing on MEBML2 as the lithography solution for 32-nm HP node and beyond is that it only needs investments on developing this tool. Unlike EUV and double patterning, which need enormous investments on the mask infrastructure and process development, besides just the cost of the lithography tool. However, the success of the MEBML2 technology still requires enormous industrial support and investments, which may happen only when it is commonly viewed as one of the mainstream technologies for high-volume manufacturing. To catch up manufacturing of the 32-nm HP node, the clustered platform has to be ready by 2012, which needs big platform suppliers' involvement very soon.
基于成熟的MEMS功能和电子技术,可以实现低成本的高通量MEBML2,在< 100 WPH和占地面积类似于光扫描仪。在如此高的吞吐量下,5 keV的分辨率,接近校正,晶圆加热和数据速率应该不是问题。专注于MEBML2作为32nm HP节点及以上光刻解决方案的另一大优势是,它只需要投资开发该工具。不像EUV和双重图案,除了光刻工具的成本之外,还需要在掩模基础设施和工艺开发上进行大量投资。然而,MEBML2技术的成功仍然需要巨大的工业支持和投资,这可能只有当它被普遍视为大批量制造的主流技术之一时才会发生。为了赶上32nm HP节点的生产,集群平台必须在2012年之前准备就绪,这需要大型平台供应商的参与。
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引用次数: 3
期刊
2009 International Symposium on VLSI Technology, Systems, and Applications
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