Ladislav Seliga, J. Pjencak, Y. Takeda, A. Hasegawa, Mitsuru Soma
{"title":"Importance of Mechanical Stress Study in STI based BCD Technology","authors":"Ladislav Seliga, J. Pjencak, Y. Takeda, A. Hasegawa, Mitsuru Soma","doi":"10.1109/ASDAM55965.2022.9966755","DOIUrl":null,"url":null,"abstract":"The paper summarizes optimization of process integration in 0.25 µm modern Bipolar-CMOS-DMOS (BCD) technology with respect to a mechanical stress induced by Shallow Trench Isolation (STI) and Resurf OXide (ROX) during manufacturing. Process optimization by TCAD simulation and silicon experiments is discussed to reduce mechanical stress in the structures and improve yield by reducing leakage current of NMOS devices. Based on simulations results, two solutions to reduce mechanical stress are proposed and evaluated in silicon experiment. The impact of integration changes to other devices in the technology is evaluated as well.","PeriodicalId":148302,"journal":{"name":"2022 14th International Conference on Advanced Semiconductor Devices and Microsystems (ASDAM)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 14th International Conference on Advanced Semiconductor Devices and Microsystems (ASDAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASDAM55965.2022.9966755","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The paper summarizes optimization of process integration in 0.25 µm modern Bipolar-CMOS-DMOS (BCD) technology with respect to a mechanical stress induced by Shallow Trench Isolation (STI) and Resurf OXide (ROX) during manufacturing. Process optimization by TCAD simulation and silicon experiments is discussed to reduce mechanical stress in the structures and improve yield by reducing leakage current of NMOS devices. Based on simulations results, two solutions to reduce mechanical stress are proposed and evaluated in silicon experiment. The impact of integration changes to other devices in the technology is evaluated as well.