Study of VCO Delay Cell Topologies in a 3-stage DR-VCO for Radiation Hardening

Abstract

Wide tuning range delay cell based 3-stage differential ring VCO designed using 90nm CMOS process operating at 2.6 GHz frequency shows better single event tolerance compared to diode-connected, triode load and Maneatis load delay cell topologies. This topology can be used in PLL and DLL clock generation applications for improved radiation tolerance for LET values between 10–50 MeV-cm2/mg.