Mario Sako, Y. Watanabe, T. Nakajima, Jumpei Sato, K. Muraoka, M. Fujiu, F. Kouno, M. Nakagawa, M. Masuda, Koji Kato, Yuri Terada, Y. Shimizu, M. Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, M. Kamoshida, M. Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita
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引用次数: 12
Abstract
The demand for high-throughput NAND Flash memory systems for mobile applications such as smart phones, tablets, and laptop PCs with solid-state drives (SSDs) has been growing recently. To obtain higher throughput, systems employ multiple NAND Flash memories operating simultaneously in parallel. The available power for a mobile device is severely restricted and the peak total operating current may be high enough to cause large supply-voltage drop or even an unexpected system shutdown. Therefore it is important for NAND Flash memories to reduce operating power and peak operating current.
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