3D simulation of charge collection and SEU of 0.13µm partially depleted SOI SRAM

Xiaochen Zhang, S. Yue, Liang Wang, Jiancheng Li
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引用次数: 3

Abstract

In this paper, the charge collection and parasitic bipolar effect of SOI NMOS devices in case of different ion strike locations have been analyzed through 3D simulation. The simulation results show that the strike at drain region can cause charge collection comparable with the collection induced by strike at the gate region above body. Single event upset (SEU) simulations of SRAM cell have been conducted. Results indicate that the reverse-biased drain region is sensitive to SEU, as well as the gate region. The largest amount of charge collection in device and the lowest LET threshold of SEU in SRAM both occur when the ion strikes at the drain/body junction area and passes through the centre part of the reverse junction.
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0.13µm部分耗尽SOI SRAM电荷收集和SEU的三维模拟
本文通过三维仿真分析了不同离子冲击位置下SOI NMOS器件的电荷收集和寄生双极效应。仿真结果表明,漏极区击击引起的电荷收集与体上栅极区击击引起的电荷收集相当。对SRAM单元进行了单事件扰动(SEU)仿真。结果表明,反向偏置漏极区和栅极区对SEU都很敏感。器件中的最大电荷收集量和SRAM中SEU的最低LET阈值都发生在离子撞击漏极/本体结区并通过反向结的中心部分时。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Defects in low-κ dielectrics and etch stop layers for use as interlayer dielectrics in ULSI Impact of body tie and Source/Drain contact spacing on the hot carrier reliability of 45-nm RF-CMOS The impact of recovery on BTI reliability assessments A novel virtual age reliability model for Time-to-Failure prediction 3D simulation of charge collection and SEU of 0.13µm partially depleted SOI SRAM
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