Kyle G. Welch, J. Monzel, D. Kent, Donald W. Joseph
{"title":"Delay testing and failure analysis of ECL logic with embedded memories","authors":"Kyle G. Welch, J. Monzel, D. Kent, Donald W. Joseph","doi":"10.1109/VTEST.1991.208167","DOIUrl":null,"url":null,"abstract":"Two delay testing techniques, 'weighted random pattern' (WRP) test for logic and 'algorithmic pattern generation at the tester' (APG @ TT) for embedded memories are discussed. Several performance fails detected with these test techniques, escaping prior tests, are presented and potential failure modes predicted. AC probing techniques used to replicate the fails during failure analysis are featured.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208167","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Two delay testing techniques, 'weighted random pattern' (WRP) test for logic and 'algorithmic pattern generation at the tester' (APG @ TT) for embedded memories are discussed. Several performance fails detected with these test techniques, escaping prior tests, are presented and potential failure modes predicted. AC probing techniques used to replicate the fails during failure analysis are featured.<>
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