Program Disturb Mechanism in Embedded SuperFlash® Technology

Abstract

In advanced embedded split-gate SuperFlash® 3rd generation technology (ESF3) the select gate is compiled with continually scaled core logic transistors. In doing so, enhanced performance and lower power are achieved. However, it was observed during ESF3 process development and integration with 1 V core logic that the program disturb performance was degraded over previous generations of this cell. Data are presented to show that the disturb phenomenon was driven by trap-assisted tunneling in the 19 Å core oxide. Corrective actions taken to eliminate this failure mechanism are discussed. Process improvement solutions were successfully applied to the smaller ESF3 technology nodes compatible with 1 V core logic and thinner gate dielectric. Pathway for continual scaling of the ESF3 cell technology in line with core transistors is presented.