Array architecture for ATG with 100% fault coverage

Abstract

Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results.<>