Circuit-level modeling of spot defects

Abstract

Describes some of the problems faced in mapping spot defects (e.g. extra/missing material, gate oxide pinholes) to changes in the nominal circuit. Traditionally, a very simple mapping has been used, with circuit faults assumed to consist of shorts, opens and occasionally, extra devices. The authors discuss some of the problems in achieving the simple mapping and how they are solved in VLASIC catastrophic fault yield simulator. They also describe modeling problems that appear to require full 3-D device simulation. Finally some investigations into the hazy boundary between parametric and functional faults are described.<>