Singular Point Source MOS (S-MOS) Cell Concept

Abstract

A Singular Point Source MOS (S-MOS) cell concept suitable for power semiconductor MOS based devices is presented. The S-MOS differs from a standard Planar or Trench MOS cell in the manner by which the total channel width per device area is determined. The S-MOS cell channel width is defined as the peripheral length of a line running approximately along the N++ source and P channel junction which is situated on a single gated trench side-wall. The length of the line can be established from a singular point source implant for forming the N++ source region which corresponds to the shape of the N++/P junction. The total channel width will therefore depend on the total number of gated trench side-walls per chip. Despite a relatively short channel width obtained on a single trench side-wall, narrow mesa dimensions between adjacent trenches will provide an adequate number of cells for adjusting the total channel width as required for a given device performance. The S-MOS can be realized by simple manufacturing processes and presents an alternative approach for MOS cell layouts by decoupling critical design parameters (e.g., channel width, trench dimension and NPN transistor area). This flexibility can lead to lower overall losses, lower gate charge levels, improved switching robustness and controllability for different MOS based devices.