Gurunath Vishwamitra Yoganath, Quang Tien Tran, Hans Ecke
Gate Controlled Diode (GCD) with micro-pattern trench structure, allows charge carrier modulation at the anode region by gate control. This is utilized to operate the diode at low saturation mode and desaturate the diode before IGBT turn-on, to achieve a better trade-off. The paper demonstrates the concept of a silicon bi-polar power diode with micro-pattern trench gate, for 6.5 kV applications. Thereby, a detailed study of switching behaviour and the switching pattern were conducted, so as to reduce the overall switching loss and improve the efficiency. The efficiency also depends on the robustness of the diode, several issues concerning the reverse recovery robustness of the Gate controlled diode were investigated.
{"title":"A Simulation study of 6.5kV Gate Controlled Diode","authors":"Gurunath Vishwamitra Yoganath, Quang Tien Tran, Hans Ecke","doi":"10.14311/isps.2021.009","DOIUrl":"https://doi.org/10.14311/isps.2021.009","url":null,"abstract":"Gate Controlled Diode (GCD) with micro-pattern trench structure, allows charge carrier modulation at the anode region by gate control. This is utilized to operate the diode at low saturation mode and desaturate the diode before IGBT turn-on, to achieve a better trade-off. The paper demonstrates the concept of a silicon bi-polar power diode with micro-pattern trench gate, for 6.5 kV applications. Thereby, a detailed study of switching behaviour and the switching pattern were conducted, so as to reduce the overall switching loss and improve the efficiency. The efficiency also depends on the robustness of the diode, several issues concerning the reverse recovery robustness of the Gate controlled diode were investigated.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125368163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we compare a new Single Active Gate Trench IGBT(SAG-IGBT) with the conventional Double Active Trench Gate IGBT (DAG-IGBT) structures with the LTO (LOCOS Trench Oxide) technology. Both structures have been fabricated with the same design rules and process platform and test chips compared in terms of their Eon performance. The new proposed SAG-IGBT is created by connected one of the active trench to emitter potential which effectively halves the gate capacitance C GE and C GD . It is also shown that the proposed SAG-IGBT can achieve a further 50% reduction in Q GC than the conventional device due to only one trench being used for MOS channel conduction per unit cell. In addition it is shown that the SAG design can improve turn-on energy loss, E ON, by up to 25% for identical Vce(on), with no degradation in the SCSOA.
{"title":"Experimental Comparison of a New SAG-IGBT and Conventional DAG-IGBT Structures with LTO Design in terms of Turn-on Performance","authors":"S. T. Kong, L. Ngwendson","doi":"10.14311/isps.2021.005","DOIUrl":"https://doi.org/10.14311/isps.2021.005","url":null,"abstract":"In this paper, we compare a new Single Active Gate Trench IGBT(SAG-IGBT) with the conventional Double Active Trench Gate IGBT (DAG-IGBT) structures with the LTO (LOCOS Trench Oxide) technology. Both structures have been fabricated with the same design rules and process platform and test chips compared in terms of their Eon performance. The new proposed SAG-IGBT is created by connected one of the active trench to emitter potential which effectively halves the gate capacitance C GE and C GD . It is also shown that the proposed SAG-IGBT can achieve a further 50% reduction in Q GC than the conventional device due to only one trench being used for MOS channel conduction per unit cell. In addition it is shown that the SAG design can improve turn-on energy loss, E ON, by up to 25% for identical Vce(on), with no degradation in the SCSOA.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115509022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Siemieniec, René Mente, M. Kutschak, F. Pulsinelli
Switched mode power supplies (SMPS) for target applications covering a wide range from telecom rectifiers through servers to solar inverters or electric vehicle chargers share the need for high efficiencies in order to minimize the overall energy consumption and the total cost of ownership. With the appearance of wide bandgap semiconductors designers cannot only choose between different devices but also may benefit from using advanced topologies. This work compares important properties of a CoolSiC ™ Silicon-Carbide MOSFET, a CoolGaN ™ E-mode GaN power transistor, a TRENCHSTOP 5 ™ IGBT accompanied by a SiC Schottky diode and a CoolMOS ™ Superjunction (SJ) device, and discusses an approach to avoid the limitations of SJ devices with respect to hard commutation of the body diode and evaluates the achievable efficiency in the AC-DC conversion stage of a power supply.
{"title":"Power device solutions for highly efficient power supplies","authors":"R. Siemieniec, René Mente, M. Kutschak, F. Pulsinelli","doi":"10.14311/isps.2021.008","DOIUrl":"https://doi.org/10.14311/isps.2021.008","url":null,"abstract":"Switched mode power supplies (SMPS) for target applications covering a wide range from telecom rectifiers through servers to solar inverters or electric vehicle chargers share the need for high efficiencies in order to minimize the overall energy consumption and the total cost of ownership. With the appearance of wide bandgap semiconductors designers cannot only choose between different devices but also may benefit from using advanced topologies. This work compares important properties of a CoolSiC ™ Silicon-Carbide MOSFET, a CoolGaN ™ E-mode GaN power transistor, a TRENCHSTOP 5 ™ IGBT accompanied by a SiC Schottky diode and a CoolMOS ™ Superjunction (SJ) device, and discusses an approach to avoid the limitations of SJ devices with respect to hard commutation of the body diode and evaluates the achievable efficiency in the AC-DC conversion stage of a power supply.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130709102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Double pulse test (DPT) is usually used to characterize and verify turn-on/turn-off operation of power switches. Yet, new high frequency switching devices based on SiC and GaN technologies require much more elaborate DPT circuitry and sensing nodes compared to the established Si devices. Especially, suitable current sensors are challenging to realize and always limit the bandwidth. We propose a Transmission Line Pulsing (TLP)-based technique, which we call sensor gap TLP (sgTLP) and which is capable to monitor the transient currents and voltages during the turn-on sequence of a power MOSFET, without the need of a current sensor. The proposed sgTLP approach is compared to established TLP methods in two applications: the passive switching of a fast transient voltage suppression diode and the active switching of a Si power MOSFET. The novel sgTLP shows the same or better characteristics than both of the standard methods, but needs only one measurement, where standard TLP would need two separate methods. Especially, sgTLP detected rise times of 54 ps of a current and 52 ps of a voltage signal using a pulse duration of 100 ns. The measured characteristics of the MOSFET turnon reveals several inductive and capacitive coupling mechanisms that are not analyzable by the established TLP methods but become visible applying sgTLP.
{"title":"Measuring Transient I/V Turn-On Behavior of a Power MOSFET without a Current Sensor","authors":"Dennis Helmut, G. Groos, G. Wachutka, G. Schrag","doi":"10.14311/isps.2021.020","DOIUrl":"https://doi.org/10.14311/isps.2021.020","url":null,"abstract":"Double pulse test (DPT) is usually used to characterize and verify turn-on/turn-off operation of power switches. Yet, new high frequency switching devices based on SiC and GaN technologies require much more elaborate DPT circuitry and sensing nodes compared to the established Si devices. Especially, suitable current sensors are challenging to realize and always limit the bandwidth. We propose a Transmission Line Pulsing (TLP)-based technique, which we call sensor gap TLP (sgTLP) and which is capable to monitor the transient currents and voltages during the turn-on sequence of a power MOSFET, without the need of a current sensor. The proposed sgTLP approach is compared to established TLP methods in two applications: the passive switching of a fast transient voltage suppression diode and the active switching of a Si power MOSFET. The novel sgTLP shows the same or better characteristics than both of the standard methods, but needs only one measurement, where standard TLP would need two separate methods. Especially, sgTLP detected rise times of 54 ps of a current and 52 ps of a voltage signal using a pulse duration of 100 ns. The measured characteristics of the MOSFET turnon reveals several inductive and capacitive coupling mechanisms that are not analyzable by the established TLP methods but become visible applying sgTLP.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124790585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. V. Treek, H. Schulze, R. Baburske, F. Hille, F. Niedernostheide, F. Pfirsch
Short-circuit behavior and capability are investigated and optimized during IGBT development. Thereby, knowledge about destruction and high-frequency short-circuit oscillation mechanisms is needed. For the thermal destruction mechanism, filaments are formed shortly before destruction during the thermal runaway itself, whereas for the electrical destruction mechanism strong current filaments are formed by an electrical mechanism, before the self-heating in the filaments leads to a thermal runaway. At low collector-emitter voltages, weak non-destructive filaments exist for a large current range. For both the filament formation and short-circuit oscillations (SCOs), an electric-field peak in the field-stop layer and a quasi-plasma layer beneath the MOS cells are mandatory. For SCOs, which are caused by a periodic storage and release of charge carriers inside the device, additionally, a weak electrical field at the beginning of the drift zone is necessary. Weak, non-destructive filaments and SCOs are likely to occur simultaneously. An increase of the bipolar current gain reduces the operating area with SCOs and increases the electrical short-circuit capability. A simultaneous reduction of the thermal short-circuit robustness can be avoided by advanced p-emitter concepts or (over-)compensated by an improved thermal setup.
{"title":"Key criteria for the short-circuit capability of IGBTs","authors":"V. V. Treek, H. Schulze, R. Baburske, F. Hille, F. Niedernostheide, F. Pfirsch","doi":"10.14311/isps.2021.001","DOIUrl":"https://doi.org/10.14311/isps.2021.001","url":null,"abstract":"Short-circuit behavior and capability are investigated and optimized during IGBT development. Thereby, knowledge about destruction and high-frequency short-circuit oscillation mechanisms is needed. For the thermal destruction mechanism, filaments are formed shortly before destruction during the thermal runaway itself, whereas for the electrical destruction mechanism strong current filaments are formed by an electrical mechanism, before the self-heating in the filaments leads to a thermal runaway. At low collector-emitter voltages, weak non-destructive filaments exist for a large current range. For both the filament formation and short-circuit oscillations (SCOs), an electric-field peak in the field-stop layer and a quasi-plasma layer beneath the MOS cells are mandatory. For SCOs, which are caused by a periodic storage and release of charge carriers inside the device, additionally, a weak electrical field at the beginning of the drift zone is necessary. Weak, non-destructive filaments and SCOs are likely to occur simultaneously. An increase of the bipolar current gain reduces the operating area with SCOs and increases the electrical short-circuit capability. A simultaneous reduction of the thermal short-circuit robustness can be avoided by advanced p-emitter concepts or (over-)compensated by an improved thermal setup.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125063429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a Short Circuit type I detection method based on the monitoring of the gate voltage is investigated. The proposed detection principle relies on an existing method, which was realized as an integrated solution before. A modified discrete circuit solution is introduced, developed and tested. Moreover, measurements and investigations on different packaging concepts and test conditions are performed. The overview of the functionality, reliability, and restraints of this method, as well as aspects of a supposed dynamic self-adaption feature, are discussed.
{"title":"Fast Short Circuit Type I Detection Method based on VGE-Monitoring","authors":"C. Herrmann, X. Liu, J. Lutz, T. Basler","doi":"10.14311/isps.2021.018","DOIUrl":"https://doi.org/10.14311/isps.2021.018","url":null,"abstract":"In this paper, a Short Circuit type I detection method based on the monitoring of the gate voltage is investigated. The proposed detection principle relies on an existing method, which was realized as an integrated solution before. A modified discrete circuit solution is introduced, developed and tested. Moreover, measurements and investigations on different packaging concepts and test conditions are performed. The overview of the functionality, reliability, and restraints of this method, as well as aspects of a supposed dynamic self-adaption feature, are discussed.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131177373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper based on the example of white power LEDs illustrates the methodology for the generation of device compact thermal models, whose element values can be assigned physical meaning. The diode thermal behaviour was studied both with the forced water cooling and with the natural convection air cooling. Moreover, owing to the fact that the investigated devices had an electrically isolated thermal pad, the measurements were carried out with the thermal pad properly soldered and with the pad left unconnected, what facilitated the identification of particular sections in the heat flow path. All the measurements of device heating or cooling curves were taken according to the JEDEC standards. The determination of the optical power allowed the computation of the real heating power, which was used then as the input quantity for thermal computations and analyses presented in this paper. Based on the measurement results, thermal structure functions and time constant spectra were computed using the Network Identification by Deconvolution method. The compact thermal models of the investigated LEDs were derived based on the time constant spectra. Owing to the proposed methodology, it was possible to attribute physical meaning to model element values. The accuracy of generated compact models was validated by comparing the simulated heating curves with the measured ones. Although the compact models for the investigated cases consisted only of four RC stages, they provided excellent simulation accuracy with errors below 4% of the maximum temperature rise value.
{"title":"Structure-Aware Compact Thermal Models of Power LEDs","authors":"K. Kuzniak, K. Szymanska, Ł. Starzak, M. Janicki","doi":"10.14311/isps.2021.022","DOIUrl":"https://doi.org/10.14311/isps.2021.022","url":null,"abstract":"This paper based on the example of white power LEDs illustrates the methodology for the generation of device compact thermal models, whose element values can be assigned physical meaning. The diode thermal behaviour was studied both with the forced water cooling and with the natural convection air cooling. Moreover, owing to the fact that the investigated devices had an electrically isolated thermal pad, the measurements were carried out with the thermal pad properly soldered and with the pad left unconnected, what facilitated the identification of particular sections in the heat flow path. All the measurements of device heating or cooling curves were taken according to the JEDEC standards. The determination of the optical power allowed the computation of the real heating power, which was used then as the input quantity for thermal computations and analyses presented in this paper. Based on the measurement results, thermal structure functions and time constant spectra were computed using the Network Identification by Deconvolution method. The compact thermal models of the investigated LEDs were derived based on the time constant spectra. Owing to the proposed methodology, it was possible to attribute physical meaning to model element values. The accuracy of generated compact models was validated by comparing the simulated heating curves with the measured ones. Although the compact models for the investigated cases consisted only of four RC stages, they provided excellent simulation accuracy with errors below 4% of the maximum temperature rise value.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133493727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-Voltage IGBT turn-off at transition from overcurrent to desaturation","authors":"Weinan Chen, Chaozheng Qin, J. Lutz, T. Basler","doi":"10.14311/isps.2021.006","DOIUrl":"https://doi.org/10.14311/isps.2021.006","url":null,"abstract":"","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129237116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Marek, J. Kozarik, A. Chvála, M. Minárik, L. Stuchlíková
{"title":"Degradation of Power SiC MOSFET under Repetitive UIS and Short Circuit Stress","authors":"J. Marek, J. Kozarik, A. Chvála, M. Minárik, L. Stuchlíková","doi":"10.14311/isps.2021.010","DOIUrl":"https://doi.org/10.14311/isps.2021.010","url":null,"abstract":"","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"7 33","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120966126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Drobný, J. Marek, A. Chvála, J. Faraga, J. Jagelka, L. Stuchlíková
This paper highlights electrically active defects investigation of the sixth generation 1200 V trench stop silicon-based Insulated Gate Bipolar Transistors by Deep Level Transient Fourier Spectroscopy. The focus is on the impact of electrical stress on defects distribution in the studied structures. Five electronlike deep energy levels ET1 (0.126 eV), ET2 (0.188 eV), ET3 (0.322 eV), ET4 (0.405 eV), and ET5 (0.514 eV), and nine hole-like deep energy levels HT1 (0.187 eV), HT2 (0.231 eV), HT3 (0.246 eV), HT4 (0.301 eV), HT5 (0.319 eV), HT6 (0.327 eV), HT7 (0.529 eV), HT8 (0.534 eV), and HT9 (0.750 eV) were identified. The presence of unintentional impurities like zinc, platinum, gold, etc. and emissions from structural imperfections was confirmed. A significant increase of the defect concentration after electrical stress in the temperature range of 120 to 225 K has been detected. Electrical stress did not affect the defect concentration above temperature 300 K.
{"title":"The influence of electrical stress on the distribution of electrically active defects in IGBT","authors":"J. Drobný, J. Marek, A. Chvála, J. Faraga, J. Jagelka, L. Stuchlíková","doi":"10.14311/isps.2021.013","DOIUrl":"https://doi.org/10.14311/isps.2021.013","url":null,"abstract":"This paper highlights electrically active defects investigation of the sixth generation 1200 V trench stop silicon-based Insulated Gate Bipolar Transistors by Deep Level Transient Fourier Spectroscopy. The focus is on the impact of electrical stress on defects distribution in the studied structures. Five electronlike deep energy levels ET1 (0.126 eV), ET2 (0.188 eV), ET3 (0.322 eV), ET4 (0.405 eV), and ET5 (0.514 eV), and nine hole-like deep energy levels HT1 (0.187 eV), HT2 (0.231 eV), HT3 (0.246 eV), HT4 (0.301 eV), HT5 (0.319 eV), HT6 (0.327 eV), HT7 (0.529 eV), HT8 (0.534 eV), and HT9 (0.750 eV) were identified. The presence of unintentional impurities like zinc, platinum, gold, etc. and emissions from structural imperfections was confirmed. A significant increase of the defect concentration after electrical stress in the temperature range of 120 to 225 K has been detected. Electrical stress did not affect the defect concentration above temperature 300 K.","PeriodicalId":125960,"journal":{"name":"ISPS'21 Proceedings","volume":"38 26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114100079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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