An A-SAR ADC circuit with adaptive auxiliary comparison scheme

Abstract

This paper extends the accelerated-SAR (A-SAR) technique, which was previously implemented in a Voltage-to-Time (VTC) based ADC circuit, to the mainstream voltage comparison based ADC circuits. In the design of VTC-based A-SAR ADC circuits, the levels for auxiliary comparison can be easily generated. However, it is more complicated to produce such auxiliary levels in the voltage comparison based circuits. Techniques to cope with this design challenge are discussed in the paper. In addition, this work further enhances the efficiency of the A-SAR technique by introducing adaptive auxiliary level selection. System-level simulations show that the proposed adaptive auxiliary level selection method significantly outperforms the previous approach that uses fixed auxiliary levels. Circuit techniques to implement the adaptive methods are also presented in the paper. The proposed method and developed circuit techniques are implemented in 10-bit ADC circuits. The performance of the A-SAR ADC is compared with a conventional SAR ADC and the comparison demonstrates the benefits of the proposed techniques.