Instruction decoders based on pattern factorization

Abstract

This work presents the design of hardware instruction decoders based on the Pattern Based Instruction Word (PBIW) encoding technique. Instruction decoder circuits have been designed in the datapath of ρ-VEX and the Leon3 soft-core embedded processors. The PBIW encoding scheme focuses on extracting out patterns from original instructions at compiler time. The PBIW hardware decoder works on the processor datapath simplifying the decoding instruction logic by exploring the hardware parallelism between instruction decoding and register read. The experiments show that the instruction decoders based on the PBIW technique present small impacts on area, dynamic power, and timing (3%-10% decrease on clock frequency) on the processor design.