KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406912

Kratika Garg, Y. Aung, S. Lam, T. Srikanthan

引用次数: 5

Abstract

FPGAs with integrated hard processors delivering a combination of performance, power savings and flexibility are becoming leading products in the market. Use of this platform calls for efficient hardware-software partitioning, which is crucial to the overall performance and reliability of these platforms. In this paper, we present a run-time efficient hardware-software partitioning technique for FPGAs called `KnapSim'. It employs two well-known heuristics - 0-1 Knapsack and Simulated Annealing algorithms, and provides near-optimal solutions. Experimental results show that performance of the proposed method is significantly better than Simulated Annealing in terms of quality of results and run-time.

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运行时高效的fpga硬件软件分区技术

具有集成硬处理器的fpga提供了性能，节能和灵活性的组合，正在成为市场上的领先产品。使用这个平台需要有效的硬件软件分区，这对这些平台的整体性能和可靠性至关重要。在本文中，我们提出了一种运行时高效的fpga硬件软件分区技术，称为“KnapSim”。它采用了两种著名的启发式算法——0-1背包和模拟退火算法，并提供了接近最优的解决方案。实验结果表明，该方法在结果质量和运行时间方面明显优于模拟退火。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 28th IEEE International System-on-Chip Conference (SOCC)

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