Fault detection in sequential circuits through functional testing

Abstract

The authors present a new functional test pattern generation algorithm for sequential architectures based on their finite state machine specification. The algorithm is based on a functional fault model. Each transition of the finite state machine is analyzed and state distinguishing sequences are adopted to observe their final state. Overlapping of test sequences is performed in order to reduce test length. Experimental results have shown the effectiveness of the test algorithm both at the functional level and at the gate level. The relations between synthesis, fault coverage and testing will be also determined.